Will Si SJ MOSFETs maintain their lead over GaN power devices? https://t.co/eEbFw1Mcvk #papers
— Wladek Grabinski (@wladek60) May 4, 2016
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May 04, 2016 at 06:58PM
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May 4, 2016
Will Si SJ MOSFETs maintain their lead over GaN power devices? https://t.co/eEbFw1Mcvk #papers
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May 04, 2016 at 06:58PM
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May 3, 2016
4th Training Course on Compact Modeling
4th Training Course on Compact Modeling
(TCCM)
in Tarragona on June 27-28 2016
The 4th TCCM is partially sponsored by the DOMINO H2020 project. It will consist a series of lectures conducted by prestigious researchers in the field of modeling of semiconductor devices, dealing with several issues related to the semiconductor device modeling, mostly compact/SPICE modeling. It is a very interesting event to PhD students and young researchers, but can interest senior researchers too.
Invited TCCM Lecturers:
Invited TCCM Lecturers:
- Morgan Madec (Univ of Strasbourg, France): Compact modeling for biological applications
- Mansun Chan (Hong Kong University of Science and Technology): An Integrated Approach for Circuit Performance and Reliability Simulation
- Mohammed Nawaz (ABB Sweden): Static and dynamic characterization of SiC based MOSFETs/IGBTs
- Christoph Jungemann (RWTH-Aachen): TCAD and semiclassical device modeling
- Antonio Cerdeira (CINVESTAV, Mexico): Model parameter extraction techniques
- Fabrizio Torricelli (Univ. of Brescia, Italy): Modelling of Amorphous-Oxide-Semiconductors TFTs for large-area flexible electronics
- Eugenio Cantatore (TU-Eindhoven): Application of compact models for organic circuit design
- Ahmed Nejim (Silvaco): TCAD for compact model development
- Firas Mohammed (Infiniscale): Mathematical and Semi-physical compact modeling for emerging technologies
- Heinz Olaf Müller (Plastic Logic): Device simulation for Organic Electronics using Genius
Besides, on June 29 1016, a Workshop on Flexible Electronics will be organized, too. Attendees to TCCM who work on Flexible Electronics (not necessarily modeling) will have a chance to present recent results on their own.
Finally, on June 30-July 1 we will organize the Annual Graduate Student Meeting on Electronic Engineering, consisting of plenary talks by prestigious researchers and student presentations.
[more about DOMINO H2020 project at ww.domino-rise.eu]
Apr 29, 2016
CMOS-SOI-MEMS Uncooled Infrared Security Sensor With Integrated Readout https://t.co/FRVIoqutaL #papers #feedly
CMOS-SOI-MEMS Uncooled Infrared Security Sensor With Integrated Readout https://t.co/FRVIoqutaL #papers #feedly
— Wladek Grabinski (@wladek60) April 29, 2016
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April 29, 2016 at 10:37PM
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Realizing Efficient Volume Depletion in SOI Junctionless FETs https://t.co/F3sOQxVV30 #papers #feedly
Realizing Efficient Volume Depletion in SOI Junctionless FETs https://t.co/F3sOQxVV30 #papers #feedly
— Wladek Grabinski (@wladek60) April 29, 2016
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April 29, 2016 at 09:52PM
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Apr 27, 2016
Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers
Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers
— Wladek Grabinski (@wladek60) April 27, 2016
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April 27, 2016 at 02:50PM
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Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers
Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers
— Wladek Grabinski (@wladek60) April 27, 2016
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April 27, 2016 at 02:50PM
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Apr 25, 2016
5 Eclipse tools for processing and visualizing data https://t.co/XNd6R5dQW3 #papers
5 Eclipse tools for processing and visualizing data https://t.co/XNd6R5dQW3 #papers
— Wladek Grabinski (@wladek60) April 25, 2016
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April 25, 2016 at 08:56PM
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Apr 23, 2016
Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs https://t.co/3hTmr2Kwmv #papers #papers
Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs https://t.co/3hTmr2Kwmv #papers #papers
— Wladek Grabinski (@wladek60) April 23, 2016
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April 23, 2016 at 01:33PM
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III–V Tunnel FET Model With Closed-Form Analytical Solution https://t.co/mExcthY64C #papers #feedly #papers
III–V Tunnel FET Model With Closed-Form Analytical Solution https://t.co/mExcthY64C #papers #feedly #papers
— Wladek Grabinski (@wladek60) April 23, 2016
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April 23, 2016 at 01:27PM
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Apr 22, 2016
#Compact #Model for MetalOxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers
#Compact #Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers
— Wladek Grabinski (@wladek60) April 22, 2016
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April 22, 2016 at 05:53PM
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Physically Based Compact Mobility Model for Organic Thin-Film Transistor https://t.co/2iRX20ogJL #papers
Physically Based Compact Mobility Model for Organic Thin-Film Transistor https://t.co/2iRX20ogJL #papers
— Wladek Grabinski (@wladek60) April 22, 2016
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April 22, 2016 at 06:39PM
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#Compact #Model for MetalOxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers
#Compact #Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers
— Wladek Grabinski (@wladek60) April 22, 2016
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April 22, 2016 at 05:53PM
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Apr 21, 2016
SPICE models for Precision DACs https://t.co/evOjXzJZYd #papers
SPICE models for Precision DACs https://t.co/evOjXzJZYd #papers
— Wladek Grabinski (@wladek60) April 21, 2016
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April 21, 2016 at 08:20PM
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Apr 19, 2016
[mos-ak] A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis
A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis
M. E. Brinson 1,* andV. Kuznetsov 2
Keywords:Qucs; Verilog-A analogue module synthesis;equation-defined devices (EDD); compact device modelling; circuit simulation
Summary: Since the introduction of SPICE non-linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE-based open source general public license circuit simulators, including Qucs, Ngspice and Xyce©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation-defined device is an extension of the SPICE style non-linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog-A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog-A model from a schematic, with embedded non-linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog-A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog-A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright © 2016 John Wiley & Sons, Ltd.
Article first published online: 15 APR 2016; DOI: 10.1002/jnm.2166
References
[1] Newton AR, Pederson DO, Sangiovanni-Vincentelli A. SPICE Version 2g User's Guide. Department of Electrical Engineering and Computer Sciences, University of California: Berkeley, CA, 1981.
Go here for SFX
[2] Johnson B, Quarles T, Newton AR, Pederson DO, Sangiovanni-Vincentelli A. Berkeley, CA. Department of Electrical Engineering and Computer Sciences, University of California, 1992.
Go here for SFX
[3] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs (Quite universal circuit simulator), 2015. Available from: http;//qucs.sourceforge.net [Accessed November 2015].
[4] Nenzi P, Vogt H. Ngspice-26 (Next generation SPICE version 26), 2015. Available from: http://ngspice.sourceforge. net. [Accessed November 2015].
[5] Sandia National Laboratories, US, Xyce parallel electronic simulator version 6.3., 2015. Available from: http: //xyce.sandia.gov.[Accessed November 2015].
[6] Jahn S, Brinson ME. Interactive compact device modelling using Qucs equation-defined devices. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2008; 21(5): 335–349.
Direct Link:
Abstract PDF(1011K) References Web of Science® Times Cited: 7 Go here for SFX
[7] Brinson ME, Jahn S. Qucs: a GPL software package for circuit simulation, compact device modelling and circuit macromodelling from DC to RF and beyond. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2009; 22(4): 297–319.
Direct Link:
Abstract PDF(1156K) References Web of Science® Times Cited: 7 Go here for SFX
[8] Accellera, Verilog-AMS Language Reference Manual. Version 2.3.1., 2009. Available from: http://www.accellera.org. [Accessed November 2015.]
[9] Silicon Integration Initiative (Si2), Compact Model Coalition, 2015. Available from: http;//www.si2.org. [Accessed November 2015.]
[10] Brinson ME, Jahn S. Modelling high-frequency inductance with Qucs non-linear radio frequency equation defined devices.International Journal of Electronics 2009; 96(3): 307–321.
CrossRef, Web of Science® Times Cited: 1
Go here for SFX
[11] Lemaitre L, Gu B. ADMS - A fully Customizable Compact Model Compiler, NSTI-Nanotech, 2008. Available from: www.nsti.org[Accessed March 2016].
Go here for SFX
[12] Lemaitre L, Grabinski W, McAndrew C. Compact device modelling using Verilog-AMS and AMS. Electron Technology (Internet Journal). June 6 2003, pp 1-5. Available from: http://www.ite.waw.pl/etij/pdf/35-03p.pdf. [Accessed November 2015.]
[13] Lemaitre L, McAndrew CM, Hamm S. Automatic Device Model Synthesis. CICC: Florida, USA, 2002.
Go here for SFX
[14] Eaton JW. GNU Octave. Version 4.0, 2015. Available from: https:www.gnu.org/software/octave/. [Accessed November 2015.]
[15] Brinson M, Crozier R, Novak C, Roucaries B, Schreuder F, Torri GT. Building a second generation Qucs GPL circuit simulator: package structure, simulation features and compact device modelling capabilities. London, 2014. Available from: http://www.mos-ak.org/london−2014/presentations/09−Mike−Brinson−MOS-AK−London−2014.pdf. [Accessed November 2015].
Go here for SFX
[16] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs: an introduction to the new simulation and compact device modelling features implemented in release 0.0.19/0.0.19Src2 of the popular GPL circuit simulator. MOS-AK ESSDERC/ESSCIRC Workshop. 18 September Graz, Austria 2015. Available from: http://www.mos-ak.org/graz−2015/presentationsT−5−Brinson−MOS-AK−Graz−2015.pdf. [Accessed November 2015].
Go here for SFX
[17] Anognetti P, Massobrio G. Semiconductor Device Modeling with SPICE. McGraw-Hill Inc: New York, 1988.
Go here for SFX
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Apr 18, 2016
CMC Leadership
CMC Leadership represents the industry’s top semiconductor design companies and manufacturers.
In their role, they provide overall direction and guidance to the efforts of the members and the developers involved in CMC working groups.
Chair: Dr. Peter Lee, Micron Technology
Vice-Chair: Dr. Josef Watts, GLOBALFOUNDRIES
Secretary Richard Williams, IBM
Treasurer: Takeshi Naito, Toshiba
In their role, they provide overall direction and guidance to the efforts of the members and the developers involved in CMC working groups.
Chair: Dr. Peter Lee, Micron Technology
Vice-Chair: Dr. Josef Watts, GLOBALFOUNDRIES
Secretary Richard Williams, IBM
Treasurer: Takeshi Naito, Toshiba
Apr 15, 2016
A review of electrical characterization techniques for ultrathin FDSOI materials and devices https://t.co/TCICVWiFdW #papers #feedly
A review of electrical characterization techniques for ultrathin FDSOI materials and devices https://t.co/TCICVWiFdW #papers #feedly
— Wladek Grabinski (@wladek60) April 15, 2016
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April 15, 2016 at 10:13PM
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A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis https://t.co/IsNSKkSLtL #papers
A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis https://t.co/IsNSKkSLtL #papers
— Wladek Grabinski (@wladek60) April 15, 2016
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April 15, 2016 at 10:12PM
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Apr 14, 2016
Characterization and modeling of drain current local variability in 28 and 14nm FDSOI nMOSFETs https://t.co/3bOVSMHjON #papers
Characterization and modeling of drain current local variability in 28 and 14nm FDSOI nMOSFETs https://t.co/3bOVSMHjON #papers
— Wladek Grabinski (@wladek60) April 14, 2016
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April 14, 2016 at 10:30PM
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