[paper] Geometrical variability in FinFETs

C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz,

Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs,

Solid-State Electronics, 2025, 109212,

ISSN 0038-1101,

DOI: 10.1016/j.sse.2025.109212.

Abstract: Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.

Keywords: Geometrical variability; Gate leakage mechanism; Direct oxide tunneling; Trap assisted tunneling; Leakage current; MS-EMC; FinFET

Fig: Schematic FinFET device herein analyzed with confinement and transport directions (011) and <011>, respectively, and all the constant and varying geometrical parameters. Although FinFET is a 3D structure, it can be studied in a 2D approach, considering high aspect ratio fins (H>>TSi). In this 2D system, x and z are the transport and confinement directions, respectively; whereas y corresponds to the infinite direction. The 1D Schrödinger equation is solved for each grid point in the transport direction, and BTE is solved by the MC method in the transport plane.

IEEE SSCS DL at NXP Semiconductors, Munich

IEEE SSCS Distinguished Lecture

at NXP Semiconductors, Munich

Alvin Loke 

"The Road to Gate-All-Around and Its Impact on Analog Design"

Date/Time: 

11 Sep 2025 04:00 PM CEST to 06:30 PM CEST

Location: 

Schatzbogen 7; Munich, Bayern, Germany 81829

Building: NXP Semiconductors Germany GmbH

Host:

Germany Section Chapter, SSC37

Co-sponsored by NXP Semiconductors

Contact:

Event Host

FREE REGISTRATION 

Abstract: Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around transistor architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. We will then shift to summarize the challenges that CMOS technology scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design closure, we will cover design strategies on how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling, including the migration to heterogeneous integration as prophesied by Gordon Moore's seminal 1965 paper.

Biography: Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel's Angstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received a B.A.Sc. in engineering physics from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford. After several years in CMOS process integration, Alvin has since worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary, SSCS Global Chapters Chair, and again as Distinguished Lecturer. Alvin has authored over 70 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. He holds 29 US patents and recently received the ISSCC 2024 Outstanding Forum Speaker Award.

[paper] An Open-Source AMS Circuit Optimization

Z. Li and A. Chan Carusone

An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning: 

From Specifications to Layouts

in IEEE Access, vol. 12, pp. 150032-150045 (2024) 

DOI: 10.1109/ACCESS.2024.3478832

Abstract: This paper presents a fully open-sourced AMS integrated circuit optimization framework based on reinforcement learning (RL). Specifically, given a certain circuit topology and target specifications, this framework optimizes the circuit in both schematic and post-layout phases. We propose using the heterogeneous graph neural network as the function approximator for RL. Optimization results suggest that it can achieve higher reward values with fewer iterations than the homogeneous graph neural networks. We demonstrate the applications of transfer learning (TL) in optimizing circuits in a different technology node. Furthermore, we show that by transferring the knowledge of schematic-level optimization, the trained RL agent can optimize the post-layout performance more efficiently than optimizing post-layout performance from scratch. To showcase the workflow of our approach, we extended our prior work to optimize latched comparators in the SKY130 and GF180MCU processes. Simulation results demonstrate that our framework can satisfy various target specifications and generate LVS/DRC clean circuit layouts.

FIG: Proposed AMS IC optimizer overview. 

The picture is adapted from [Z. Li and A. C. Carusone; 2023]

Acknowledgment: The authors would like to thank Dr. Hossein Shakiba from Huawei Technologies
for his valuable discussions throughout this project.

[REF] Z. Li and A. C. Carusone, "Design and optimization of low-dropout voltage regulator using relational graph neural network and reinforcement learning in open-source SKY130 process," in Proc. IEEE/ACM Int. Conf. Comput. Aided Design (ICCAD), Oct. 2023, pp. 1–9.

[mos-ak] Join the ICMC 2026 Organizing Team

International Compact Modeling Conference (ICMC) 2025 was a great success - thank you to everyone who contributed!  We're excited to announce that preparations are already underway for the next edition, taking place July 30–31, 2026 in Long Beach, California.

We are currently seeking enthusiastic volunteers to join the ICMC2026 organizing committees. If you're interested in helping shape next year's event, please complete the survey linked below:

https://survey.zohopublic.com/zs/bQfsUq

Submission deadline: August 25, 2025

📩 For questions about available roles, feel free to contact:

Shahed Reza, ICMC2026 General Chair or

Gert-Jan Smit, ICMC2026 Technical Program Chair

We look forward to your participation!

Thank you,
Leigh Anne Clevenger , Si2, on behalf of the ICMC2026 Organizing Committee

[mos-ak] [Final Program] 9th Sino MOS-AK Workshop Shenzhen

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

9th Sino MOS-AK Workshop Shenzhen

August 14-16, 2025

We are pleased to invite you to participate in the 9th Sino MOS-AK Workshop, a premier forum for researchers, engineers, and industry professionals engaged in the device simulations, compact modeling, Verilog-A standardization, and advanced circuit design. This year's workshop will be hosted at SUSTech in Shenzhen, offering a dynamic program that blends cutting-edge research with practical insights. 

Venue:

• Southern University of Science and Technology (SUSTech), Shenzhen, China

Workshop Agenda <https://www.mos-ak.org/shenzhen_2025/>

• Aug.14 Room 103
• Tutorial: Millimeter-wave Radar Technologies for Future Smart Home Applications
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45275
• Aug.15 Room 103
• Special Session: Advanced GaN Device Modeling and Circuit Design
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45275
• Aug.15 Room 104
• Special Session: Artificial Intelligence in Device Modeling and Circuit Design
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45276
• Aug.16 Room 103
• Special Session: Device Modeling and Circuit Designs for Extreme Temperatures
• 深圳器件模型国际会议 access link：https://www.koushare.com/live/details/45275
• Aug.16 Graduate Student Poster Session

We look forward to your participation in this vibrant exchange of ideas and innovations. For registration and inquiries, please contact: music@sustech.edu.cn

-- Min Zhang and W.Grabinski on the behalf of International MOS-AK TPC Committee

---

Enabling Compact Modeling R&D Exchange

www.mos-ak.org

---

WG11082025

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[book] Guide to Characteristics and Characterization of Semiconductor Surfaces

Guide to Characteristics and Characterization 

of Semiconductor Surfaces

By: Jerzy Ruzyllo (Penn State University, USA)

https://doi.org/10.1142/12792 | May 2025 | Pages: 220

This comprehensive compendium explores aspects of semiconductor surface characteristics and characterization from the perspective of applied semiconductor device research and process development, rather than an in-depth coverage of surface science related issues. It provides guidance to the features of semiconductor surfaces affecting performance of the practical semiconductor devices, as well as selection of methods used to characterize those features.

Based on the author's over thirty years of research and graduate advising in semiconductor surface processing and characterization, this unique reference text addresses the needs of graduate students, researchers and industry professionals who are familiar with semiconductor engineering and would like to learn about the practical aspects of semiconductor surface characteristics, processing techniques, and characterization methods used in device process development, process diagnostics and monitoring.

• FRONT MATTER i–xv
• Chapter 1: Surface as a Part of Semiconductor Device Material System 1–14
• Chapter 2: Effect of Surface on Characteristics of Semiconductor Materials 15–36
• Chapter 3: Interactions of Semiconductor Surfaces 37–56
• Chapter 4: Characteristics of Semiconductor Surface Defining its Condition 57–68
• Chapter 5: Surface Effects in Semiconductor Devices 69–79
• Chapter 6: Surface Processing in Semiconductor Device Technology 81–117
• Chapter 7: Semiconductor Surface Characterization Methods 119–152
• Chapter 8: Characterization of Semiconductor Surfaces in Process Monitoring 153–176
• BACK MATTER 177–201

[mos-ak] IEEE SSCS-EDS South Brazil Chapter DL - IHP OpenPDK Initiative – Technology · Devices · Applications

The IEEE SSCS-EDS South Brazil Chapter, chaired by Juan Pablo Martinez Brito, PhD, to host Wladek Grabinski, PhD, a global expert in SPICE modeling and open-source IC design, for a Distinguished Lecture:

IHP OpenPDK Initiative – Technology · Devices · Applications

Date: August 13th, 2025

Time: 14h00 (GMT-3, Brasília)

IEEE SSCS-EDS South Brazil Chapter YouTube Channel

http://www.youtube.com/c/sscsedssouthbrazil

Dr. Grabinski will explore the growing role of FOSS CAD/EDA tools and OpenPDKs in strengthening the semiconductor ecosystem and enabling accessible IC design worldwide.

Thanks to the support of Unisinos, Federal University of Rio Grande do Sul, and UNIPAMPA Universidade Federal do Pampa RS, and to all the volunteers and engineers helping grow our regional chapter. Also, thank you to the chapter Board: Sandro Binsfeld Ferreira, Tiago Oliveira Weber, and Paulo César C. de Aguirre, and Professors Gilson Wirth and Sergio Bampi for the advice.

Looking forward to engaging with students, researchers, and professionals from across Brazil and beyond.

Attachments:

Event Calendar Invite

 Add Event to Calendar

 iCal
 Google Calendar

South Brazil Section Jt. Chapter,SSC37/ED15

#OpenPDK #SPICE #CompactModeling #Semiconductors #IEEE #ICDesign #FOSS #AnalogDesign #PDK #CMOS #IHP #SkyWater #GF #EDA #SouthAmericaSemiconductors #MOSAK #EDS #SSCS #UFRGS #Unisinos #Unipampa

WG060825

Low Cost Open Source MPW Access with IHP 130nm BiCMOS OpenPDK

Low Cost Open Source MPW Access 

with IHP 130nm BiCMOS OpenPDK

Terms and conditions
The mentioned prices below refer to the open-source designs, where all the views are compatible with the open source EDA tools.

For customers who do not wish to disclose their IP, we offer participation in the OpenMPW program at a 20% discount off the regular price, as the wafers can be shared with other customers. The turn around processing time is approx. 6 months for SG13CMOS and 8 months for SG13G2. Our/IHP basic offer contains 20 bare die samples. It is also possible to rent the wafer for measurements. Packaging will be offered on request (additional fee can be applied). 

Request/reserve your MPW IC Chip area online

Date of the upcoming MPW tapeout:  Optional run in November 2025, SG13CMOS

Total amount used by all customers: tbd

Price per mm²:

SG13CMOS – the initial price is 1500 EUR/mm² and it will scale down to 1000 EUR/mm² 

if the total area requested by all customers will be higher than 150 mm²

SG13G2 – fully featured G2 with AL BEOL at approx. 2800 EUR/mm²

SG13G2 Technology overview:

• High speed SiGe HBT's featuring transit frequency (fT) of 350 GHz
• Low/High voltage CMOS devices
• 78 standard cells, IO-cells, a few fixed size SRAM
• Regular ESD diodes, NMOS clamps
• S-varicap
• Schottky diodes
• Polysilicon resistors, tap devices
• MIM capacitor
• 7 layer aluminium BEOL with 2 thick 3um top metal layers
• [NB] SG13CMOS does not provide HBT's

IHP-Open-PDK Overview

• Symbols for Xschem/Qucs-S
• Ngspice models
• Xyce models
• Klayout support for layout, PyCells, DRC and LVS
• Magic basic support (more to be finished until the end of the year)
• OpenROAD-flow-script support
• OpenEMS EM solver support
• Measurements RAW data in MDM format

Click here to open the IHP 130nm BiCMOS Open Source PDK documentation link

<https://ihp-open-pdk-docu.readthedocs.io/en/latest/index.html>

Click here to open the standard MPW price information

<https://www.ihp-microelectronics.com/services/research-and-prototyping-service/mpw-prototyping-service/schedule-price-list>

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