Showing posts with label Double-Gate (DG) Tunnel-FET. Show all posts
Showing posts with label Double-Gate (DG) Tunnel-FET. Show all posts

Feb 22, 2018

[paper] TFET Devices Re-Evaluation Résumé

Capturing Performance Limiting Effects in Tunnel-FETs
Michael Graef1,2, Fabian Hosenfeld1,2, Fabian Horst1,2, Atieh Farokhnejad1,2
Benjamín Iñíguez2 and Alexander Kloes1
1Competence Centre for Nanotechnology and Photonics, THM, Giessen, Germany
2DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
ISTE OpenScience DOI: 10.21494/ISTE.OP.2018.0220

Abstract: In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior of the TFET is shown. In focus of this work are the emerging variability issues with this new type of device. Random-dopant-fluctuations (rdf) have a major influence on the device performance. This effect is analyzed and compared with rdf effects in a MOSFET device. The drawn conclusions lead to a re-evaluation of performance limiting aspects of fabricated TFET devices [read more: 10.21494/ISTE.OP.2018.0220]

 FIG: a) Schematic geometry of an n-type DG Tunnel-FET, showing its structural parameters and doping profiles. b) Schematic band structure of a n-Tunnel-FET showing the different operating regimes and their dominating currents.