1260 Reads:
Open-source circuit simulation tools for RF compact semiconductor device modelling
Feb 7, 2017
[paper] Impact of technology scaling on analog and RF performance of SOI–TFET
Impact of technology scaling on analog and RF performance of SOI–TFET
P Kumari, S Dash and G P Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4
Published 9 October 2015
Abstract
This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD Sentaurus device simulation results [read more...]
Citations
[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al 2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al 2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al 2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al 2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al 2015 447
Feb 5, 2017
[paper] Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers
Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers
S. Golara, S. Moloudi and A. A. Abidi, "
in IEEE Transactions on Circuits and Systems I: Regular Papers,
vol. 64, no. 2, pp. 245-260, Feb. 2017; doi: 10.1109/TCSI.2016.2604000
Abstract:
Using an appropriate formulation of field-effect transistor (FET)
current as a nonlinear function of terminal voltages, and a simplified
model of gain compression in common source amplifiers, we are able to
identify four principal sources of amplitude-to-phase (AM-PM)
distortion. A new analysis shows the varactor effect of gate-source
capacitance on AM-PM distortion, and the changing Miller-multiplied
gate-drain capacitance as the field-effect transistor (FET) is driven
into compression. The phase shift in the load impedance at the frequency
of operation and incomplete suppression of 2nd harmonic by a resonant
load of limited Q are explained and analyzed. We are able to identify
the dominant mechanism of AM-PM distortion in various practical
circuits, which then suggests methods of remediation. The analysis was
put to test by predicting the measured AM-PM distortion of power
amplifiers reported in the literature. Good agreement is found in all
cases, with insights gained into the dominant cause of distortion in
each case. In this paper, AM-PM distortion is first defined in Section II. In Section III, the EKV model of the MOSFET is briefly presented and dominant mechanisms are explained. In Section IV the analysis is compared against measured data to validate the theory and Section V summarizes the conclusions [read more...]
Feb 1, 2017
IEEE Workshop on Compact Modeling
IEEE Workshop on Compact Modeling
March 3, 2017
Technical Sponsorship by: IEEE Electron Devices Society UP Chapter
Organized by: Department of Electrical Engineering, IIT Kanpur
Coordinator: Prof. Yogesh Singh Chauhan
Venue: Outreach Auditorium, IIT Kanpur
Time | Topic | Speaker |
---|---|---|
8:00 - 8:15 | Workshop inauguration by Director IIT Kanpur and IEEE-UP Chairman | |
8:15 - 9:00 | Industry Standard Compact Modelling | Dr. Yogesh Singh Chauhan IIT Kanpur |
9:00 - 9:30 | Modelling of mismatch and process variations | Dr. Abhisek Dixit IIT-Delhi |
9:30 - 10:00 | TBA | Dr. Nihar Ranjan Mohapatra IIT-Gandhinagar |
10:00 - 10:30 | Modelling of normally-off GaN based MOSHEMT | Dr. Trupti Ranjan Lenka NIT Silchar |
10:30 - 10:45 | ASM-HEMT: Industry standard compact model for GaN HEMTs | Dr. Sudip Ghosh IIT-Kanpur |
10:45 - 11:00 | Modelling of quasi ballistic transport in nano-wire transistors | Mr. Avirup Dasgupta IIT Kanpur |
11:00 - 11:15 | TBA | Mr. Priyank Rastogi IIT Kanpur |
11:15 - 11:30 | Compact modelling of TMD based thin body transistors | Mr. Chandan Yadav IIT Kanpur |
11:30 - 11:45 | Tea Break | |
11:45 - 12:15 | Qualification techniques for sim models for EEsof products | Mr. Mohit Khanna Keysight Technologies |
12:15 - 12:45 | High frequency device characterization and modeling for THz applications | Prof. Thomas Zimmer IMS-BORDEAUX |
12:45 - 2:00 | Lunch | |
2:00 - 2:30 | Device design consideration: IoT perspective | Dr. Santosh Kumar Vishvakarma IIT-Indore |
2:30 - 3:00 | TBA | Dr. Aditya Sankar Medury IISER-Bhopal |
3:00 - 3:30 | Simulations, analysis and applications of doping- and junction- free transistors | Dr. Jawar Singh IIIT-Jabalpur |
3:30 - 4:00 | Design of radiation hardened 24-bit ADC for generic applications | Mr. H.S.Jattana SCL |
4:00 - 4:15 | Tea Break | |
4:15 - 4:45 | Role of Feynman diagrams in energy band structure of materials - A post density functional theory approach | Dr. Sitangshu Bhattacharya IIIT-Allahabad |
4:45 - 5:15 | TBA | Dr. Swaroop Ganguly IIT-Bombay |
5:15 - 5:45 | TBA | Dr. Saurabh Lodha IIT-Bombay |
5:45 - 6:15 | TBA | Dr. Udayan Ganguly IIT-Bombay |
6:15 - 6:45 | TBA | Dr. Manoj Saxena Delhi University |
6:45 - 7:00 | Closing Keynote |
Labels:
compact modeling,
EDS,
IEEE,
workshop
Location:
Kanpur, Uttar Pradesh, India
Jan 31, 2017
#Memristors, the fourth fundamental circuit element? https://t.co/V03Zp7Oaxw #cad #feedly #papers
#Memristors, the fourth fundamental circuit element? https://t.co/V03Zp7Oaxw #cad #feedly #papers
— Wladek Grabinski (@wladek60) January 31, 2017
from Twitter https://twitter.com/wladek60
January 31, 2017 at 02:53PM
via IFTTT
[chapter] Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing
Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing
Massimo Alioto
Department of Electrical & Computer Engineering, National University of Singapore
in Enabling the Internet of Things; pp 95-148
DOI: 10.1007/978-3-319-51482-6_4
This chapter addresses the challenges and the opportunities to perform computation with nearly-minimum energy consumption through the adoption of logic circuits operating at near-threshold voltages. Simple models are provided to gain an insight into the fundamental design tradeoffs. A wide set of design techniques is presented to preserve the nearly-minimum energy feature in spite of the fundamental challenges in terms of performance, leakage and variations. Emphasis is given on debunking the incorrect assumptions that stem from traditional low-power common wisdom at above-threshold voltages. The traditional EKV model is very useful for quick estimates, but it oversimplifies the IV characteristics that is observed in actual nanometer CMOS technologies [read more...]
Labels:
CMOS,
ekv,
IV,
minimum energy,
subthreshold
Location:
Singapore
[paper] Electronically tunable MOSFET-based resistor
Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter
W. L. Tan, C. H. Chang and L. Siek
Nanyang Technological University; Singapore
2016 International Symposium on Integrated Circuits (ISIC), Singapore, 2016, pp. 1-4.
doi: 10.1109/ISICIR.2016.7829715
Abstract: We present a new design of an electronically tunable linear MOS resistor circuit that operates in the subthreshold saturation region, supported with mathematical derivations and simulation results using CSM0.13µm technology. For a given potential difference across the MOS resistor, its gate voltage will be automatically biased through feedback to provide the correct amount of current based on the desired resistance set through the bias current. Equating the output current of the OTA with the subthreshold equation of the EKV model. In comparison with an existing design, the proposed design offers equal tunabilty with 36 less transistors for unidirectional current and 28 less transistors with one more bias current transistor for bidirectional current. A bias current ranging between 10nA to 100nA offers a tunable linear resistance between 20MΩ to 140MΩ [read more...]
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