[paper] Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

Aishwarya Natarajan and Jennifer Hasler

Georgia Institute of Technology Atlanta USA

Analog Integr Circ Sig Process (2017), pp 1–12

doi:10.1007/s10470-016-0914-y

ABSTRACT: An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process [read more...]

On Layout Tools and others

A while ago SolvEx Group has posted a blog note on the Layout Tools, including the open source ones, too. There are also a few questions which are worth to review again:

1. How is Layout different from Placement and Route?
2. What is the difference between Synopsys Astro and Cadence Virtuoso-do they offer layout or are just placement and routing tools? (Comparing them with Magic and LASI)!
3. What is the intermediate map/snapshot/diagram - which we can use and create a complete chip out of? For example after seeing the Chip and reverse engineering the same- what is that something which I can use to create my own chip in the foundry? Reference - Chinese Mobile chips. They do the same-as they bypass the flow for design entry/verification/simulation/floor planning etc and release the chip within a few hrs of seeing the original chip(say famous case of duplicating iPhone/Nokia in the Chinese markets)
4. Are Stick Diagrams passed to the Foundry or else what is the base unit that is given to Foundry as an input to be manufactured as a chip.
5. Giving below a collection all possibly available Layout Tools (Categorized as Open Source, Cheap, Expensive)

Open source software	Description	Web site
wol	Wol is a graphical environment for IC mask layout	http://www.cs.berkeley.edu/~lazzaro/chipmunk/describe/wol.html
toped	Micron based layout editor with extensive scripting capabilities. Under active development and part of Fedora Electronic Lab.	http://www.toped.org.uk
microwind3	Lambda based layout editor especially adapted for interactive design with Spice. This used to be completely free, but now only a Lite version is.	http://www.microwind.org
magic	Lambda based layout editor with good options for writing CIF and/or GDS files. Supports scripting. Large user base. Part of Fedora Electronic Lab. Used for extraction and CIF/GDS creation by the pharosc libraries	http://opencircuitdesign.com/magic
lasi	LASI stands for LAyout Software for Individuals. It is designed to run on Windows, though it also runs on Linux under Crossover Office. Actively used software with frequent updates.	http://lasihomesite.com
kic	Part of open source packages released by Whiteley Research.	http://wrcad.com/freestuff.html
graal	Lambda based layout editor allowing conversion to CIF and GDS with appropriate technology files. Dreal is the companion software to view CIF and GDS. Part of a tool set from Alliance which is probably the best open-source software for IC design. Comes with own standard cell library. Part of Fedora Electronic Lab. The pharosc standard cells are drawn with graal.	http://www-asim.lip6.fr/recherche/alliance
electric	Comprehensive set of software programs designed around the concept of silicon compilation. Version 6 crashed a lot, and stored all design data in a single file which exposed one to the risk of file corruption and loss of all data (I speak from experience). New version written in Java. Extensive documentation.	http://www.staticfreesoft.com/productsSoftware.html
dreal	Simple layout editor which uses CIF or GDS as its native format. Companion software is Graal.	http://www-asim.lip6.fr/recherche/alliance
Cheap software
xic	Whiteley Research Inc. Layout editor with linked Spice simulator. List price is $1195.	http://www.wrcad.com/xic.html
slam-edit	Stabie-Soft Inc. Unix/Linux based layout editor. It seems a licence cannot be purchsed, only leased for one year periods (bad if the company folds). List price on web site is $2,000 per year.	http://www.stabie-soft.com/sledit.html
ledit	Tanner Research Inc. Windows only layout editor popular with mixed signal designers. Ledit sed to cost $1,000, but this price could not be verified (which is surprising since low price is a key selling point of the software).	http://www.tanner.com/EDA/product/Tools_PhysicalLayout.html
layedpro	Mycad Inc. Windows only layout editor designed in Korea but supported for English language users from California. No new product since 2005 on US site, but Korean site seems active. No price could be confirmed.	http://www.mycad.com/02pro/01.html http://www.mycad.co.kr
layed	Catena Software GmbH. Demo versions for Linux and Windows can be downloaded. List price of the basic editor might be €1,585 (could not be recently verified).	http://www.catena-ffo.de/laytools.htm
iced	IC Editors Inc. Windows only editor that used to cost $2,750. Now it is free but with a restrictive licence. Work is on-going to open source it which might make it available under Linux (although the Windows drawing primitives would need to be replaced with GTK).	http://www.iceditors.com
Expensive software
virtuoso	Cadence Design Systems, Inc. The market leader. The price might be $40,000 to lease for one year.	http://www.cadence.com/products/custom_ic/veditor/index.aspx
max	Micro Magic Inc. Looks like a commercial version of Magic. Price is $30,000 for a one year licence. Despite the fancy price tag, something was freely downloadable from the web in the 2004 timeframe.	http://www.micromagic.com
laker	Silicon Canvas Inc. Linux and Unix based editor. Top of the line laker-ddl is $70,000 for a one year licence. Regular Laker 3 is $35,000 for a one year licence.	http://www.sicanvas.com
icstation	Mentor Graphics Corp. No public pricing information could be found.	http://www.mentor.com/cicd/icstation.html

FOSS CAD research is in the spotlight

The conference paper "FOSS as an efficient tool for extraction of MOSFET compact model parameters" reached 20 reads at the researchgate.net

FOSS as an efficient tool for extraction of MOSFET compact model parameters

D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski

MIXDES 2016, Lodz, pp. 68-73.

doi: 10.1109/MIXDES.2016.7529702

Abstract—A GNU Octave – based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV. Selected aspects of the application are presented and discussed. 

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers

Ken Shirriff Takes Us Inside the IC, For Fun https://t.co/QScTdhgFXV #papers

— Wladek Grabinski (@wladek60) December 27, 2016

from Twitter https://twitter.com/wladek60

December 27, 2016 at 09:24PM
via IFTTT

J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers

J-EDS Comes of Age https://t.co/4HNl9cQhzh #papers

— Wladek Grabinski (@wladek60) December 27, 2016

from Twitter https://twitter.com/wladek60

December 27, 2016 at 01:07PM
via IFTTT

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly

Special Issue of Solid-State Electronics, dedicated to EUROSOI-ULIS 2016 https://t.co/fFD9GehZEP #papers #feedly

— Wladek Grabinski (@wladek60) December 25, 2016

from Twitter https://twitter.com/wladek60

December 25, 2016 at 09:14PM
via IFTTT

[paper] Analysis and Compact Modeling of Negative Capacitance Transistor

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current
and Negative Output Differential Resistance
Part II: Model Validation

Girish Pahwa, Student Member, IEEE, Tapas Dutta, Member, IEEE, Amit Agarwal,
Sourabh Khandelwal, Member, IEEE, Sayeef Salahuddin, SM IEEE,
Chenming Hu, IEEE Fellow, and Yogesh Singh Chauhan, SM IEEE 

in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016

doi: 10.1109/TED.2016.2614436

Abstract: In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.

[read more at IEEE Xplore]