From YahooFinance: (see their page for the original post)
Synopsys, Inc. (SNPS),
a global leader providing software, IP and services used to accelerate
innovation in chips and electronic systems, today announced immediate
availability of its comprehensive solution for FinFET-based
semiconductor designs. The solution includes a range of DesignWare®Embedded Memory and Logic Library IP; silicon-proven design tools from the Galaxy™
Implementation Platform; and foundry-endorsed extraction, simulation
and modeling tools. It also includes TCAD and mask synthesis products
used by foundries for FinFET process development. The three-dimensional
structure of FinFET devices represents a significant change in
transistor manufacturing that impacts design implementation tools,
manufacturing tools and design IP. Developed over a period of five years
through engineering collaboration with leading foundries, research
institutes and early adopters, Synopsys' FinFET solution delivers
production-proven technologies to manage the change from planar to 3-D
transistors. The full-line solution provides a strong foundation of EDA
tools and IP needed to accelerate deployment of FinFET technology which
offers improved power, performance and area for semiconductor designs.
"Synopsys continues to make significant investments to develop a
complete solution for adoption of new process geometries and devices,
including FinFETs," said Antun Domic, senior vice president and general
manager of Synopsys' Implementation Group. "Synopsys' extensive
collaboration with all the partners within the FinFET ecosystem,
including foundries, early adopters and research institutions, allows us
to deliver best-in-class technologies and to enable the market to
realize the full potential of this new transistor design."
"With our new 14nm-XM offering, we have accelerated our leading-edge
roadmap to deliver a FinFET technology optimized for the expanding
mobile market," said Gregg Bartlett, senior vice president, chief
technology officer at GLOBALFOUNDRIES. "Collaboration with partners has
been a key element of our ability to deliver this innovative FinFET
solution. We have collaborated early with Synopsys in multiple areas,
including modeling of the FinFET devices in HSPICE. We continue our
collaboration to accelerate adoption of FinFET technology for our mutual
customers."
"Our FinFET collaboration with Synopsys is key to maintaining our
semiconductor leadership position," said Dr. Kyu-Myung Choi, senior vice
president of System LSI Infrastructure Design Center, Samsung
Electronics Co., Ltd. "Our foundry and semiconductor design expertise,
combined with Synopsys' broad EDA tool and IP development experience
enabled us to address FinFET-related challenges effectively. We continue
to engage in strong collaboration to maximize the benefits of FinFET
technology."
"Very early on, we successfully demonstrated the power and
performance benefits of using FinFET 3-D transistors," said Dr. Chenming
Hu, distinguished professor of microelectronics at University of
California, Berkeley, widely regarded as the pioneer of FinFET
technology. "To make these demonstrations possible, my team worked
closely with Synopsys R&D on a number of areas including device
simulation. We continue to collaborate with Synopsys to deliver more
innovations for FinFET deployment."
FinFET-ready IP Working closely with leading foundries
for more than five years enabled Synopsys to gain design expertise and a
deep understanding of IP architectures. This close collaboration has
resulted in the successful deployment of Synopsys' DesignWare Embedded
Memory and Logic Library IP solutions on FinFET to key customers. A
broader range of IP is planned for development in 2013. The DesignWare
Embedded Memory and Logic Library IP is architected to achieve the full
benefits of the FinFET technology, delivering superior results in the
areas of performance, leakage and dynamic power, and low voltage
operation.
FinFET-ready Design Tools The shift from planar to
FinFET-based 3-D transistors is a significant change that requires close
R&D collaboration among tool developers, foundries and early
adopters to deliver a strong EDA foundation. Developed through a
multi-year collaboration with FinFET ecosystem partners, Synopsys'
solution accelerates time to market of FinFET-based designs. The
comprehensive solution includes IC Compiler for physical design, IC
Validator for physical verification, StarRC™ for parasitic extraction, SiliconSmart for characterization, CustomSim™ and FineSim for FastSPICE simulation and HSPICE® for device modeling and circuit simulation.
FinFET-ready Manufacturing Tools The small geometries
and 3-D nature of FinFETs require new approaches to optimize device
performance and leakage, and to address the effect of process
variations. Target device performance and leakage is achieved through
the optimization of the fin geometry, stress engineering and other
factors. Process variations stem from random dopant fluctuations, line
edge roughness, layout-induced stress and other sources, which together
impact device and circuit performance. Synopsys has been collaborating
with foundries on the Sentaurus™ TCAD and Proteus™
mask synthesis products to address these issues. The Sentaurus product
line enables foundries to optimize FinFET processing and design devices
that meet the performance and leakage targets while mitigating the
impact of process variation. The Proteus product line provides foundries
with a comprehensive solution for performing full-chip proximity
corrections.
Jan 28, 2013
Jan 27, 2013
[mos-ak] C4P: Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013
Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich <http://www.mos-ak.org/munich_2013/>
Venue:
Lehrstuhl fur Technische Elektronik
Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>
Technische Universitat Munchen
Arcisstr. 21 D-80333 Munchen
Important Dates:
- Call for Papers - Jan. 2013
- 2nd Announement - Feb. 2013
- Final Workshop Program - March, 2013
- MOS-AK/GSA Workshop - April 11-12, 2013
R&D topics to be covered include the following:
- Advances in semiconductor technologies and processing
- Compact Modeling (CM) of the electron devices
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- CM of passive, active, sensors and actuators
- Emerging Devices, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and IC Designs
- Foundry/Fabless Interface Strategies
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Jan 17, 2013
SPICE Models No Longer Only A Foundry’s Worry
A nice post at chipdesign:
By Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc.
By Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc.
SPICE Models Play a Critical Role in Both Modeling and Design Communities
Circuit
designers work with foundry libraries to evaluate a foundry process
before they run real circuit designs. It, therefore, becomes necessary
to understand the models and use them properly. Complexities of modern
libraries have made it inefficient or almost impossible to understand
them by browsing into the files.
A library can easily contain
many different sections besides core models in a macro (sub-circuit)
format, such as multiple corner model sections, statistical model
sections, mismatch model components, models for layout dependent
effects and reliability models. Without a good understanding of those
details, simulations by combining those model sections may lead to
inaccurate results.
Second, foundry models often are not built
for specific applications. Design companies are investing in SPICE
models by doing model validations, customizing models for specific
needs or even building their own models. High-end systems-on-chip
(SoCs) are now integrating more functionalities and may have different
operation modes, evaluated by performance, power, area, lifetime, cost
(yield) and time to market.
Design specifications are tougher,
but the room to maneuver has shrunk. One set of generic models can’t
meet the requirements for all different applications. Thus, it’s
worthwhile for design companies to identify the real needs of their
applications, then work with foundries or third parties or build their
own capabilities to make model libraries more application specific and
provide more value for their designs.
Third, the key motivation
for a circuit designer to understand foundry model libraries is the
impact of process variations on circuit performance and yield. Although
process engineers have tried different ways to mitigate variation
sources during manufacturing, some remain in a design that are
fundamental and must be managed during different design stages,
including global and local random variations or LDE.
Designers
can only cross their fingers if they do not know the possible results
before tapeout. Modeling engineers have figured out ways to model those
systematic and random variation effects. The next step is to apply
that information and analyze the impact to a design.
Strain
engineering improves device performance, but leads to the strong layout
dependence of device characteristics. Designers then need to consider
the impact of LDE during pre-layout design, layout design, LVS
extraction and post-layout verifications. Understanding the LDE based
on the models would help designers better optimize area versus
performance, and reduce differences between pre- and post-layout
designs to shorten design time.
Increasing random variations,
especially the local mismatch for paired transistors, affect the final
chip yield and performance. Traditional PVT analysis and selective
Monte Carlo analysis give limited information that can help achieve
chip’s functionalities, but not the possible yield or performance
distributions.
A reliable and practical design for yield (DFY)
flow with fast and accurate statistical simulation engine is required.
Moreover, before using DFY tools for yield analysis targeting yield and
performance trade-off, designers need to know how corner models and
statistical models are defined. Otherwise analysis results, based on
improper use of the variation models, will offer the wrong direction
for design optimizations.
... read more at the source...
Compact model Engineer job in IBM India (Bangalore)
For nearly 30 years, IBM has been at the forefront of
technology innovation for semiconductor solutions. IBM has transformed
semiconductor design and manufacturing with world-renowned research and
development. Our contributions are recognized throughout the industry.
Reduced Instruction Set Computing (RISC), Copper Interconnects, Silicon
Germanium (SiGE) and Silicon on Insulator (SOI) are some of the
innovations that have come from IBM.
IBM Semiconductor Research & Development centre
is expanding its operations by opening a CMOS development &
enablement group at ISL, Bangalore. Mentioned below are some of the
key areas which will be operational out of India centre.
Compact Model Development in Bulk, SOI & SiGe Technology
- Develop Core model Extraction for FET, HBT, passive devices
- Develop Extraction Algorithms (Genetic, IC-CAP, MATLAB)
- Model Build in BSIM, PSP, MEXTRAM & HiCUM
- Enable SPECTRE, HSPICE, POWERSPICE, VERILOG-A Models for Leading Design Environments
- Enable IBM Server & High-Speed-Serial Group and other Leading Customers to Design in IBM Technology
Skills important to the area:
- Knowledge of BSIM, UTMOST and / or IC-CAP MOSFET parameter Extraction
- Knowledge of Hspice / Spectre and / or PowerSpice
- Basic understanding of semiconductor device physics and operation
- Cadence Design systems and tool for programming, layout and simulation
- Software Skills - C, Java, Scripting and/or other automation languages
- We are looking for people holding a PhD / MTech / BTech in the ECE/EE/CSE disciplines.
Relevant vacancies:
SWG-0050763 | Compact Model Engineer |
---|
How to apply:
Go to the career section in their homepage...Jan 16, 2013
New IC-CAP with GaN and Python support
Some news from EDN:
Agilent Technologies recently announced a new version of IC-CAP (integrated circuit characterization and analysis platform) for high-frequency device characterization and modeling, offering parameter extraction, data analysis, instrument control and interface responsiveness. This announcement actually includes two noteworthy topics: GaN and Python.
Angelov-GaN is an industry-standard compact device model for GaN semiconductor devices. Since GaN devices typically operate at high power, it is important to be able to model thermal issues and their impacts on device characteristics. Designers working with GaN quickly realized that GaAs models were not good enough. Fortunately, Prof. I. Angelov at Chalmers University of Technology developed his Angelov-GaN model as an alternative.
In its IC-CAP 2013.01, Agilent has fully embraced the Angelov model with the W8533 Angelov-GaN extraction package. An interface lets users execute a step-by-step extraction flow to obtain model parameters. A turnkey flow aims to provide a quick-start modeling of GaN devices. Roberto Tinti, device modeling product manager with Agilent EEsof EDA explained that the company developed the extraction package in conjunction with some Japanese and US GaN partners, but he was unable to reveal company names.
read more from the original...
Agilent Technologies recently announced a new version of IC-CAP (integrated circuit characterization and analysis platform) for high-frequency device characterization and modeling, offering parameter extraction, data analysis, instrument control and interface responsiveness. This announcement actually includes two noteworthy topics: GaN and Python.
Angelov-GaN is an industry-standard compact device model for GaN semiconductor devices. Since GaN devices typically operate at high power, it is important to be able to model thermal issues and their impacts on device characteristics. Designers working with GaN quickly realized that GaAs models were not good enough. Fortunately, Prof. I. Angelov at Chalmers University of Technology developed his Angelov-GaN model as an alternative.
In its IC-CAP 2013.01, Agilent has fully embraced the Angelov model with the W8533 Angelov-GaN extraction package. An interface lets users execute a step-by-step extraction flow to obtain model parameters. A turnkey flow aims to provide a quick-start modeling of GaN devices. Roberto Tinti, device modeling product manager with Agilent EEsof EDA explained that the company developed the extraction package in conjunction with some Japanese and US GaN partners, but he was unable to reveal company names.
read more from the original...
ASP-DAC 2013 CALL FOR PARTICIPATION
Asia and South Pacific Design Automation Conference 2013
Pacifico Yokohama, Yokohama, JAPAN
January 22 - 25, 2013
http://www.aspdac.com/aspdac2013
WEB REGISTRATION DUE!!!: *** Jan. 17, 2013 ***
Please check the Registration Page:
For technical program, Please check the following link:
ASP-DAC 2013 is the eighteenth in a series of annual international conference on VLSI design automation. Asia and South Pacific region is one of the most active regions of design and fabrication of silicon chips in the world. The conference aims are providing the Asian and South Pacific CAD/DA and Design community with opportunities of interchanging ideas and collaboratively discussing the directions of the technologies related to all of Electronic Design Automation (EDA).
I N D E X [1] Keynote Speeches
[2] Designers' Forum
[3] Special Sessions
[4] Technical Sessions
[5] Tutorial
[1] Keynote Speeches
We have three keynote speakers from industry.
Keynote I : Wednesday, January 23, 8:30-10:00
"From Circuits to Cancer"
Dr. Sani Nassif, IBM
Keynote II : Thursday, January 24, 9:00-10:00
"Gearing Up for the Upcoming Technology Nodes"
Dr. Kee Sup Kim, Samsung Electronics
Keynote III : Friday, January 25, 9:00-10:00
"Human, Vehicle and Social Infrastructure System Development for
Sustainable Mobility - Development Innovation based on Large-Scale
Simulation -"
Dr. Hiroyuki Watanabe, Toyota Motor Corp.
[2] Designers' Forum
Designers' Forum is conceived as a unique program that shares the design experience and solutions of real product developments among LSI designers and EDA academia/developers. Admission fee is included in the Conference registration fee. Registration for Designers' Forum only is also available.
5A January 24, 13:40-15:40
Invited Talks: "Heterogeneous Devices and Multi-Dimensional Integration Design Technologies"
(Sony, Tokyo Inst. of Tech., TSMC, STARC, IMEC)
6A January 24, 16:00-18:00
Panel Discussion: "Future Direction and Trend of Embedded GPU"
(Panasonic, Kyushu Univ., ARM, Intel, Digital Media Professionals,
Fujitsu Lab.)
8A January 25, 13:40-15:40
Invited Talks: "Photonics for Embedded Systems"
(Hitachi, Luxtera, NEC, PETRA)
9A January 25, 16:00-18:00
Panel Discussion: "Harmonized Hardware-Software Co-design and Co-verification"
(STARC, Fujitsu Lab., Renesas, Tokyo Inst. of Tech., RWTH Aachen Cadence, Synopsys)
[3] Special Sessions
1D January 23, 10:20-12:20
University LSI Design Contest (Presentation + Poster Discussion)
21 designs are selected from 36 designs from five countries/areas.
1A January 23, 10:20-12:20
Invited Talks: "Advanced Modeling and Simulation Techniques for
Power/Signal Integrity in 3D Design"
(San Diego State Univ., Shizuoka Univ., KAIST, National Taiwan Univ.)
2A January 23, 13:40-15:40
Invited Talks: "Dependability of on-Chip Systems"
(Karlsruhe Inst. of Tech., Kyoto Univ., UC Irvine, UCLA)
3A January 23, 16:00-18:00
Invited Talks: "Design Automation for Flow-Based Microfluidic Biochips: Connecting Biochemistry to Electronic Design Automation"
(Ritsumeikan Univ., National Cheng Kung Univ., NAIST,
Tech. Univ. of Denmark, UC Riverside)
4A January 24, 10:20-12:20
Invited Talks: "High-Level Synthesis and Parallel Programming Models for FPGAs"
(Altera Toronto Technology Center, Advanced Digital Sciences Center,
Univ. of Illinois, Urbana-Champaign)
4D January 24, 10:20-12:20
Invited Talks: "Emerging Security Topics in Electronic Designs and Mobile Devices"
(Air Force Research Lab., New York Univ., UCLA, Univ. of Pittsburgh, Rutgers Univ.)
7A January 25, 10:20-12:20
Invited Talks: "Many-Core Architecture and Software Technology"
(Kyushu Univ., Univ. of Electro-Communications, Ritsumeikan Univ.,
Fixstars Corp., Fixstars Multicore Lab., TOPS Systems Corp.)
[4] Technical Sessions
97 papers are selected from 311 submissions for regular presentation
that cover key topics from system design to physical design. For
more details, please see the Home page:
http://www.aspdac.com/aspdac2013/technical_program/
[5] Tutorial
On January 22, five two-hour tutorials are scheduled, which will provide the audience with an introduction to hot topics in Embedded Multicore Programming, Pulse Based Design, Non-volatile System, Dependable Embedded Systems and RF-MEMs. Each tutorial will be presented twice a day to allow attendees to cover multiple topics. If you register for tutorials, you have the option to select three out of the five topics. Access to electronic files of tutorial presentations and a lunch coupon is included in Tutorial fee.
Tutorial-1 January 22, 9:30 - 11:30, 13:00 - 15:00
Programming Embedded Multiprocessor Systems: Application Code Mapping
and Performance Estimation Technologies
Tutorial-2 January 22, 9:30 - 11:30, 15:30 - 17:30
Pulse Based Design and Optimization
Tutorial-3 January 22, 13:00 - 15:00, 15:30 - 17:30
Temperature- and Process Variation-Aware Dependable Embedded Systems
Tutorial-4 January 22, 9:30 - 11:30, 13:00 - 15:00
Non-Volatile Memory Based Design
Tutorial-5 January 22, 13:00 - 15:00, 15:30 - 17:30
Introduction to RF CMOS and MEMS Design
Home page: http://www.aspdac.com
Sponsored by: ACM SIGDA, IEEE CASS, IEICE ESS, IPSJ SIGSLDM
Technical co-sponsor: IEEE CEDA
Japan Electronics Show Association(JESA)
1-1-3, Otemachi, Chiyoda-ku, Tokyo, 100-0004, Japan
Tel: 81-3-6212-5231 Fax: 81-3-6212-5225
E-mail: aspdac2013@aspdac.com
Jan 9, 2013
10th IWCM Workshop Program
10th International Workshop on Compact Modeling
January 22 (Tue), 2013
Pacifico Yokohama, Room 419
Yokohama, Japan
Time
|
#
|
Title
|
Authors
|
Affiliation
|
9:00-9:10
|
Opening:
H. J. Mattausch (Workshop Chair)
|
|||
Power Devices Chair: D. Navarro
|
||||
9:10-9:30
|
1
|
HiSIM_HV
Temperature Modeling for Multi-Geometry LDMOS: Comparison of the Temperature
Flag Options
|
Y.
Iino
|
Silvaco Japan
|
9:30-9:50
|
2
|
Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV
|
T.
Umeda et al.
|
Hiroshima
University
|
9:50-10:10
|
3
|
Floating-Base
Effect Modeling for IGBT Structure using Potential Modification
|
T.
Yamamoto
et al.
|
Denso
|
10:10-10:30
|
-
Break -
|
|||
Novel FET Structures Chair: T. Nakagawa
|
||||
10:30-10:50
|
4
|
Study
on Dynamic Threshold Nanowire Tunnel FET
|
A.
Zhang et al.
|
Peking
University
Shenzhen
|
10:50-11:10
|
5
|
A DC Model of TFETs for SPICE Simulations
|
L. Zhang and M. Chan
|
HK UST
|
11:10-11:30
|
6
|
A
Surface Potential Based Compact Model of Organic Thin-Film Transistor for
Circuit Simulation
|
T.K. Maiti et al.
|
Hiroshima University
|
11:30-11:40
|
- Break -
|
|||
Optical and Wireless Chair: J. He
|
||||
11:40-12:00
|
7
|
An
Embedded Modulation of Silicon Germanium FIN-LED - A simulation study
|
J.
Kwon et al.
|
Seoul
National
University
|
12:00-12:20
|
8
|
Predicting
Key Parameters of Inductive Power Links
|
S.
Raju et al.
|
HK UST
|
12:20-14:00
|
-
Lunch Break -
|
|||
Aging and Degradation Chair: M.
Miura-Mattausch
|
||||
14:00-14:40
|
9
|
Invited
Keynote: Interaction of Bloch Carrier and Bound State in the Reliability
Modeling
|
Y.J.
Park and
S.
Choi
|
Seoul
National
University
|
14:40-15:00
|
10
|
Development
of Unified Predictive NBTI Model and its Application for Circuit Aging
Simulation
|
C. Ma
et al.
|
Hiroshima
University, STARC
|
15:00-15:20
|
11
|
Effects
of Nonlocal Concentration of Carriers in the Oxide for NBTI Simulation
|
S. Rhee et al.
|
Seoul
National
University
|
15:20-15:40
|
- Break -
|
|||
Fabrication Variation Chair: Y. J. Park
|
||||
15:40-16:00
|
12
|
Parameter
Extraction for Statistical Variation of HV-MOSFETs
|
Y.
Ueda et al.
|
Ricoh, STARC
|
16:00-16:20
|
13
|
Analysis
of Gate-Length Dependence of MOSFET Random Variation by Using
HiSIM-RP
|
S.
Kumashiro
et al.
|
Renesas
Electronics
|
16:20-16:40
|
14
|
Random
Dopant Fluctuation Effects on Double Gate Tunneling FET Performance
|
Y. Zhu
et al.
|
Peking
University
Shenzhen
|
16:40-16:50
|
Closing:
H.J. Mattausch (Workshop Chair)
|
Labels:
CAD,
compact modeling,
device modelling,
EDA,
Japan,
semiconductor,
workshop
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