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Mar 17, 2021
[Workshop] Democratizing IC Design, April 7th, 2021
[C4P] ISPS 2021 Prague, August 25–27, 2021
15th INTERNATIONAL SEMINAR ON POWER SEMICONDUCTORS
ISPS 2021
Prague, 25 August – 27 August 2021
| Organised by | IET Czech Network in co-operation with the IEEE Czechoslovakia Section |
| Co-sponsored by | Faculty of Electrical Engineering, Department of Electrotechnology, Czech Technical University in Prague |
| Technical sponsor | ECPE European Center for Power Electronics e.V. |
| Conference website | http://technology.fel.cvut.cz/ISPS2021 |
BACKGROUND
The 15th International Seminar on Power Semiconductors (ISPS 2021) provides a forum for technical discussion in the area of power semiconductor devices and their applications. It is a small conference with the special flair of an atmosphere of searching deeper insight and intensive discussion.
AREAS OF INTEREST
- Power semiconductor devices (materials, physics, modelling, technology, diagnostics)
- Packaging, advanced device applications, reliability
Papers oriented in the field of power semiconductors are supposed to be presented in sessions on
- Device Physics and Technology
- Power Bipolar Devices
- Voltage-Controlled Power Devices
- Wide Bandgap Power Devices
- Power Integration
- Advanced Applications
- Packaging, Reliability & Modelling.
A round table discussion oriented on topical problems of research and education in the field of power semiconductors will be organised in the framework of the seminar.
PAPER SUBMISSION
A summary of 300–500 words (maximum two pages including figures and tables) is required for review. It should be uploaded in electronic format (.doc or .pdf files) to the ISPS 2021 easychair conference system:
http://easychair.org/conferences/?conf=isps2021
before April 30, 2021.
PUBLICATION
Presented papers will be published in the seminar proceedings, which will be distributed at the seminar registration. We are delighted to announce that the best papers presented at the conference will be invited for consideration in a special issue of the IET Power Electronics Journal dedicated to the ISPS 2021 seminar.
ORGANISING COMMITTEE
| Chairman: | Prof Vítězslav Benda, FIET |
| Members: | Dr Vítězslav Jeřábek, MIET |
| Dr Martin Molhanec | |
| Dr Ladislava Černá, MIET | |
| Dr Pavel Hrzina |
Mar 16, 2021
Nine out of ten #chips used by #US industries are made outside the country
[https://t.co/iJTj8FNNaJ] Nine out of ten #chips used by #US industries, including automotive and defense, are made outside the country https://t.co/91uq9m2VLA#semi pic.twitter.com/jhWxs4YDy5
— Wladek Grabinski (@wladek60) March 16, 2021
from Twitter https://twitter.com/wladek60
March 16, 2021 at 11:12AM
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Mar 15, 2021
[paper] 3D integrated GaN/RF-SOI SPST switch
Frédéric Drillet, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar and Gregory U'Ren
RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch
International Journal of Microwave and Wireless Technologies, pp. 1–6, 2021.
*X-FAB France, Corbeil-Essonnes (F)
Abstract: This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.
Fig: X-FAB 3D integration proposal cross-section (left) and the picture of a GaN coupon (right).
Acknowledgement: We would like to acknowledge the Nano2022 program for partially funding this work.
Supplementary material: The supplementary material for this article can be found at DOI: 0.101/1759078721000076
#SMIC reported to regain license to receive process equipment
[https://t.co/4cRTlKFKn6] #SMIC reported to regain license to receive #14nm and older process equipment https://t.co/BR3CexZKHP #semi pic.twitter.com/xybYUjI6MM
— Wladek Grabinski (@wladek60) March 15, 2021
from Twitter https://twitter.com/wladek60
March 15, 2021 at 11:46AM
via IFTTT
[ElectronicsB2B] #China Semiconductor Trade Association #CSIA Establishes Work Group With Semiconductor Industry Association #SIA #semi #feedly https://t.co/ZaWL8q2vqJ https://t.co/aZF0Ihuimb
[ElectronicsB2B] #China Semiconductor Trade Association #CSIA Establishes Work Group With Semiconductor Industry Association #SIA #semi #feedly https://t.co/ZaWL8q2vqJ pic.twitter.com/aZF0Ihuimb
— Wladek Grabinski (@wladek60) March 15, 2021
from Twitter https://twitter.com/wladek60
March 15, 2021 at 11:36AM
via IFTTT
[lectronics Weekly] #TSMC said to be planning $35bn #Arizona #Gigafab #semi https://t.co/pYLE1kdtDb https://t.co/YflKAcwTaa
[lectronics Weekly] #TSMC said to be planning $35bn #Arizona #Gigafab #semi https://t.co/pYLE1kdtDb pic.twitter.com/YflKAcwTaa
— Wladek Grabinski (@wladek60) March 15, 2021
from Twitter https://twitter.com/wladek60
March 15, 2021 at 11:22AM
via IFTTT
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