[paper] Vectorizing Device Model Evaluation in Ngspice

Vectorizing Device Model Evaluation in Ngspice circuit simulator

Florian Ballenegger, Anamosic Ballenegger Design

Preprint July 2020

Abstract: A method improving the execution speed of electrical circuit simulation using vector processing is proposed. The BSIM3V32 semi-conductor device model for the open-source Ngspice simulator has been re-written for evaluating multiple device instances of the same model at once using Single Instruction Multiple Data (SIMD) processor instructions. While parallel evaluation of device model was already available using multiprocessing, the proposed method can achieve the same speed-up using less processor resources, thus allowing to do more parallel independent simulations for statistical analysis.

In Conclusion: Only the BSIM3V32 device model was modified to use vector processing. Other device models would of course also benefit from the proposed method. In particular interest would be the EKV model https://github.com/ekv26/model, as the calculations in this symmetric model are more linear with fewer conditional branches and could be vectorized more efficently.  The source code of the modified BSIM3V3 model is available at https://www.anamosic.com/pages/ngspice.html

Softbank talks to #Apple and #Nvidia about #Arm sale https://t.co/pgShLwpAz1 #semi https://t.co/KOS9UIIhO1

Softbank talks to #Apple and #Nvidia about #Arm sale https://t.co/pgShLwpAz1 #semi pic.twitter.com/KOS9UIIhO1

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U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ #semi https://t.co/Zxeyxds702

U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ#semi pic.twitter.com/Zxeyxds702

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#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O #paper

#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O#paper

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[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.

[paper] Compact Model of All-Optical-Switching Magnetic Elements

J. Pelloux-Prayer¹ and F. Moradi¹

Compact Model of All-Optical-Switching Magnetic Elements

IEEE TED, vol. 67, no. 7, pp. 2960-2965, July 2020

DOI: 10.1109/TED.2020.2991330.

¹Department of Engineering, Aarhus University, 8200 Aarhus, Denmark

Abstract: We present, for the first time, a Verilog-A compact model for an all-optically switchable magnetic tunnel junction (MTJ) using results of all-optical-switching (AOS) simulations. Our model is compatible with electronics and photonics design automation tools, and was tested using Cadence Specter and Virtuoso. This compact model can be used to design circuits and systems combining MTJs, photonic circuits, and electronic circuits giving the possibility to researchers working within this field to develop novel circuits and systems.

Fig: Equivalent circuit of the AOS model with LLGS module and LUT module.

Aknowledgement: This work was supported by the European Union’s Horizon 2020 Research and Innovation Programme under Grant 713481.

[paper] LF Noise Characterization of Ge n-Channel FinFETs

Alberto V. de Oliveira (Member, IEEE), Duan Xie (Member, IEEE), Hiroaki Arimura, Guillaume Boccardi, Nadine Collaert, Cor Claeys (Fellow, IEEE), Naoto Horiguchi (Member, IEEE)

and Eddy Simoen (Senior Member, IEEE_

Low-Frequency Noise Characterization of Germanium n-Channel FinFETs

IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2872-2877, July 2020

DOI: 10.1109/TED.2020.2990714

Abstract: This article presents an experimental, room temperature, low-frequency noise characterization of germanium n-channel fin-field-effect transistors (finFETs) integrated on silicon. After determining the dominant mechanism in the noise spectrum, the main parameters associated with the noise mechanism are extracted and evaluated as a function of fin width from a planar-like (100 nm) up to narrow fin (20 nm) for 1-µm length devices. The main findings are that the 1/f noise plays an important role in the Ge n-finFETs, whereby the trap density profiles in the gate-stack are quite uniform and have a lower level than in n-/p-channel Ge planar MOSFETs. In addition, a generation-recombination (GR) component was found in 160-nm-length devices, which is caused by GR centers located in the depletion region.

Fig: (a) Schematic of the Ge  n-finFET structure 

and (b) gate-stack composition

Fig: Drain current noise power spectral density as a function of frequency 

for a 160nm long Ge n-finFET

Acknowledgment: The authors would like to thank the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) and the Logic IIAP program for the support. This work has been performed in the frame of the imec Core Partner program on Ge devices.