[June 18] Silicon Chip Industry Awareness Workshop

Silicon Chip Industry Awareness Workshop Seminar

Last Chance To Register ... Unlock Your Potential Today!

Join us on Tue 18 June at the Holiday Inn in Kensington, London, England, 9:30am to 4:00pm. Whether you are a non-technologist struggling with the jargon or a specialist looking to understand the overall industry structure, this workshop is for you.

Don't take our word for it … ask our past attendees. "Thank you for such an insightful class yesterday. It was the most useful training session I have had. I learned an incredible amount and I appreciate your time. What is so exciting about this field is that it is not only a lesson in physics but also chemistry, history, philosophy, geography, economics and so on."

Gain a competitive edge in the Semiconductor Industry by learning how the IC industry works from the science that enables silicon chips to be made from sand to the market fundamentals that drive applications and economics. Experience the industry through Listen, Discuss, See, Touch, and Learn activities and enjoy improved job satisfaction and operational efficiency.

Priced at just UK£795 plus 20 percent UK VAT per delegate, the fee includes copies of presentation materials, coffee breaks and lunch.  Workshops can also be held in-house for your added convenience and flexibility.  To preserve course integrity, space is limited, so don't wait – Secure Your Spot Today at: https://www.futurehorizons.com/page/12/silicon-chip-training

Past Attendee Comments
* "As a non-technologist, it was very beneficial to have these issues so clearly explained"
* "The seminar provided a good basis to understanding the industry"
* "It was GREAT! I can't remember a day of a similar density"
* "I finally understand how to recognize products & their use in technology"
* "This has helped me structure my thoughts & plans for the company"
* "It gave me deeper insight into the industry in a way difficult to obtain anywhere else"
* "This will be very useful when involved in our core business development discussions"

Book Your Place by Email

Please pass to your HR Department or a colleague if already attended or not suitable for you.

-- Sincerely -- Malcolm Penn, Chairman & CEO; 

Future Horizons; Registered Company: 4380991
Blakes Green Cottage, Sevenoaks, Kent TN15 0LQ, England
Tel: +44 (0)1732 740440

Follow us on Twitter @Future_Horizons and 

join our Linked In Group (http://uk.linkedin.com/in/malcolmpenn) 

and receive regular industry news, information and comments. 

[paper] CMOS-First MEMS-last integration

Aron Michael, Ian Yao-Hsiang Chuang, Chee Yee Kwok and Kazuo Omaki

Low-thermal-budget electrically active thick polysilicon for CMOS-First MEMS-last integration

Microsystems & Nanoengineering (2024) 10:75

DOI: 10.1038/s41378-024-00678-5

* UNSW, Sydney, NSW 2052, Australia

Abstract: Low-thermal-budget, electrically active, and thick polysilicon films are necessary for building a microelectromechanical system (MEMS) on top of a complementary metal oxide semiconductor (CMOS). However, the formation of these polysilicon films is a challenge in this field. Herein, for the first time, the development of in situ phosphorus-doped silicon films deposited under ultrahigh-vacuum conditions (~10E−9 Torr) using electron-beam evaporation (UHVEE) is reported. This process results in electrically active, fully crystallized, low-stress, smooth, and thick polysilicon films with low thermal budgets. The crystallographic, mechanical, and electrical properties of phosphorus-doped UHVEE polysilicon films are studied. These films are compared with intrinsic and boron-doped UHVEE silicon films. Raman spectroscopy, X-ray diffraction (XRD), transmission electron microscopy (TEM) and atomic force microscopy (AFM) are used for crystallographic and surface morphological investigations. Wafer curvature, cantilever deflection profile and resonance frequency measurements are employed to study the mechanical properties of the specimens. Moreover, resistivity measurements are conducted to investigate the electrical properties of the films. Highly vertical, high-aspect-ratio micromachining of UHVEE polysilicon has been developed. A comb-drive structure is designed, simulated, fabricated, and characterized as an actuator and inertial sensor comprising 20-μm-thick in situ phosphorus-doped UHVEE films at a temperature less than 500°C. The results demonstrate for the first time that UHVEE polysilicon uniquely allows the realization of mechanically and electrically functional MEMS devices with low thermal budgets.

Fig: Comb-drive fabrication: a Grow oxide; b deposit thick UHVEEPolySi; c electrical pads patterned; d pattern the comb-drive; e backside pattern; f DRIE of UHVEEPolySi; g STS ICP oxide and DRIE from backside; h Remove Cr using O2 plasma; i HF vapor etch

Acknowledgements: The authors wish to acknowledge the Australian National Fabrication Facility (ANFF) NSW node, the School of Photovoltaic & Renewable Energy Engineering (SPREE) and the Electron Microscope Unit at UNSW, where fabrication and film characterization were conducted. In addition, the authors acknowledge the financial support received from the School of Electrical Engineering & Telecommunications (EE) and UNSW Sydney.

[book] Advanced Nanoscale MOSFET Architectures

Advanced Nanoscale MOSFET Architectures:

Current Trends and Future Perspectives

Kalyan Biswas, Angsuman Sarkar

John Wiley & Sons - Technology & Engineering (2024) 336 pages

ISBN: 978-1-394-18894-9

Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation. Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs.

Table of Contents:

[1] Emerging MOSFET Technologies; pp. 1

Kalyan Biswas and Angsuman Sarkar

[2] MOSFET: Device Physics and Operation; pp. 15

Ruthramurthy Balachandran, Savitesh M. Sharma, and Avtar Singh

[3] High-k Dielectrics in Next Generation VLSI/Mixed Signal Circuits; pp. 47

Asutosh Srivastava

[4] Consequential Effects of Trap Charges on Dielectric Defects for MU-G FET; pp. 61

Annada S. Lenka and Prasanna K. Sabu

[5] Strain Engineering for Highly Scaled MOSFETs; pp. 85

Chinmay K. Maiti, Taraprasanna Dash, Jhansirani Jena, and Eleena Mohapatra

[6] TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer; pp. 113

Yash Pathak, Kajal Verma, Bansi Dhar Malhotra, and Rishu Chauzar

[7] Electrically Doped Nano Devices: A First Principle Paradigm; pp. 125

Debarato D. Ray, Pradipta Roy, and Debashis De

[8] Tunnel FET: Principles and Operations; pp. 143

Zahra Ahangari

[9] GaN Devices for Optoelectronics Applications; pp. 175

Nagarajan Mohankumar and Girish S. Mishra

[10] First Principles Theoretical Design on Graphene-Based Field-Effect Transistors; pp. 201

Yoshitaka Fujimoto

[11] Performance Analysis of Nanosheet Transistors for Analog ICs; pp. 221

Yogendra R Pundir, Arvind Bisht, and Pankaj K. Pal

[12] Low-Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode; pp. 255

Soumya Pandit and Koyel Mukherjee

[13] Ultra-conductive Junctionless Tunnel FET-based Biosensor with Negative Capacitance; pp. 281

Palasri Dhar, Soumik Poddar, and Sunipa Roy

[14] Conclusion and Future Perspectives; pp. 301

Kalyan Biswas and Anqsuman Sarkar

[INDEX]; pp. 311

[Libre Silicon] Free Semiconductors For Everyone

Libre Silicon aims to take an active role in driving forward the change and reaching the objectives outlined before. Considering the fact that the free and open-source silicon ecosystem is growing explosively since the second half of the 2010s, many of the objectives are addressed already by others. In these cases, Libre Silicon wants to support their effort and adapt their results, without aiming at realizing the same goal differently, thus preventing the fragmentation of the ecosystem. In other topics, however, there is either no progress or the progress is not going in the desirable direction. In these cases, Libre Silicon takes a leading role, using the fullest possible extent of our expertise, commitment and resources. Our focus topics, without particular order, are the following:

• Develop free technology nodes, including manufacturing recipes, test structures, primitive devices, logic, padrings, analog and other libraries, characterization methodology, and PDK support.
• Drive the adoption of these nodes, by providing the necessary documentation, consulting and technical support. Libre Silicon also aims to set the example to follow by being early adopters of our own technology nodes, including the provision of actual manufacturing service.
• Elaborate novel business models to support the emergence of universal and affordable access to semiconductor technologies. This includes, among others, novel manufacturing operation organization concepts, throughput optimization for low-volume or high-volume production, and the introduction of new, connected manufacturing concepts and equipment.
• Develop novel manufacturing equipment enabling low-volume-capable, high-flexibility manufacturing, with primary focus on maskless lithographic technologies.

In addition to these efforts, Libre Silicon also aims at providing valuable contribution to the efforts of others with shared goals, including:

• Drive the necessary paradigm shift by advocating for free and open-source silicon solutions in real-life applications
• Support the education on IC design-related skillset by taking active role in the formation of training materials, supporting and organizing events like Hackathons or workshops and mentoring
• Support the development of EDA tools by advising on, and contributing to, the development of FOSS IC design software
• Increase the scope and quality of available free silicon IP libraries by developing our own libraries and contributing to the development of others

Libre Silicon roadmap is the following:

• Establishment of LibreSilicon Foundation in Europe
• Finish LS1U technology node (incl. SPICE parameter extraction)
• Development of ESD protection and pad cell library for LS1U
• Development of a maskless lithography stepper
• Tech Demo: LS555 (design, MLL fabrication, testing)
• Digital cell library for 1u MFS + digital tools (maybe parallel to LS1U/LS555)
• Tech demo II: 8-bit Arduino-compatible MCU
• To open Libresilicon Fabrication Service in EU
• Development of LS130 technology node (incl. MLL capability)
• Tech demo III: 130nm System-on-Chip
• Development of sub-100nm technology node (incl. MLL capability)
• Tech demo IV: SOC made on LibreSilicon runs GNU/Linux
• Successful tapeout of the Danube with Global Foundries. The first successful tapeout of the new autogenerated process verification wafer Danube River

Contact -> Lebre Silicon

[paper] Półprzewodnikowa rewolucja w domenie open source

Krzysztof Herman and Anna Sojka-Piotrowska

Półprzewodnikowa rewolucja w domenie open source

https://bit.ly/IHPOpenPDK

* IHP GmbH – Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Niemcy

Abstract: Hasło „open source” kojarzy się większości osób przede wszystkim z oprogramowaniem tworzonym przez pasjonatów informatyki i udostępnianym za darmo ogólnoświatowej społeczności użytkowników. Nie mniej interesująca jest jednak grupa otwartych rozwiązań sprzętowych, czyli open source hardware – mało kto wie, że istnieją już bezpłatne pakiety oprogramowania przeznaczonego do projektowania układów scalonych, w tym nawet układów ASIC o paśmie rzędu setek GHz. Jeszcze większym zaskoczeniem może być fakt, że fabryki półprzewodników otwierają swoje podwoje także dla małych firm, partnerów akademickich, a nawet... odbiorców prywatnych! (czytaj dalej...)

Rys: Zestaw narzędzi open source do projektowania układów analogowych 

z uwzględnieniem pasma RF

Kontakt: dr Krzysztof Herman, dr Anna Sojka-Piotrowska

Ważne linki:

• IHP-Open-PDK https://github.com/IHP-GmbH/IHP-Open-PDK
• Free Silicon Foundation https://wiki.f-si.org/
• FOSSi Foundation https://fossi-foundation.org/
• eFabless  https://efabless.com
• Open Source Silicon @slack https://open-source-silicon.slack.com