[paper] Differential Aging-Aware Static Timing Analysis

Lomash Chandra Acharya, Neha Gupta, Khoirom Johnson Singh, Mahipal Dargupally, Neeraj Mishra, 

Arvind Kumar Sharma, Ajoy Mondal, Venkatraman Ramakrishnan, 

Sudeb Dasgupta, and Anand Bulusu

DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin

in IEEE Transactions on Device and Materials Reliability

DOI: 10.1109/TDMR.2025.3603098

1.) Department of Electronics and Communication Engineering, IIT Roorkee (IN)
2.) Department of Electronics, Dhanamanjuri University, Imphal (IN)
3.) Department of Electronics and Electrical Engineering, BITS Pilani (IN)
4.) Semiconductor Technology and Systems Department, IMEC (B)
5.) EDA Group, Texas Instruments, Bengaluru (IN)
6.) OnSemi Technology, Bengaluru (IN)

Abstract : This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.

FIG: Representation of the approach used to model a standard cell 

with transistor topology of a buffer and its terminal transitions as a test case.

[Education Corner] Tinkering with CMOS Circuits

P. Kinget

Tinkering with CMOS Circuits at the Lunch Table with MOSbius

[Education Corner]

in IEEE Solid-State Circuits Magazine, vol. 17, no. 3, pp. 72-78, Summer 2025

doi: 10.1109/MSSC.2025.3583537

Abstract: Experimental validation is a critical step in any engineering discipline and doing lab experiments is an essential part of the formation of an engineer. Creating relevant experiments to train integrated-circuit designers has become difficult due to the lack of appropriate components. We designed the MOSbius chip and adapter PCB so learners can perform circuit labs with MOS transistor topologies that are relevant to modern transistor-level IC design. With MOSbius, students can experiment with customized CMOS circuits early on – without the challenges, delays, and cost of designing a custom integrated circuit. Yet, MOSbius serves as a great steppingstone towards full custom IC design courses.

Fig: An overview of the MOSbius platform. Students design and realize transistor-level MOS circuits

using on-chip-style topologies and evaluate them experimentally.

Acknowledgment: Many thanks to the MOSbius crew of enthusiastic current and former students: Longyi Li, Yunfan Gao, Zhuo Chen, Petar Barac, Ray Xu, Hongzhe Jiang, Cade Gleekel, Nico de la Cruz, Rosnel Alejandro Leyva-Cortes, Yuechen He, Jingde Hu, Qizhe Wu, Jingrui Li, Xianglin Pu, Yuntao Guo, and Andrew Chon. Thanks to Apple, Inc. for fabrication funding through the Columbia ELEN E6350 VLSI Design Lab course. Thanks to Yannis Tsividis (Columbia), John Pigott (NXP), Babak Soltanian (Tayen.Ai), Jianxun Zhu (Analog Devices, Inc.), Jared Zerbe (Apple), Eric Smith (Apple), Doug Mercer (ADI), and many others for engaging discussions and sharing of ideas.

[paper] Geometrical variability in FinFETs

C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz,

Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs,

Solid-State Electronics, 2025, 109212,

ISSN 0038-1101,

DOI: 10.1016/j.sse.2025.109212.

Abstract: Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.

Fig: Schematic FinFET device herein analyzed with confinement and transport directions (011) and <011>, respectively, and all the constant and varying geometrical parameters. Although FinFET is a 3D structure, it can be studied in a 2D approach, considering high aspect ratio fins (H>>TSi). In this 2D system, x and z are the transport and confinement directions, respectively; whereas y corresponds to the infinite direction. The 1D Schrödinger equation is solved for each grid point in the transport direction, and BTE is solved by the MC method in the transport plane.

IEEE SSCS DL at NXP Semiconductors, Munich

IEEE SSCS Distinguished Lecture

at NXP Semiconductors, Munich

Alvin Loke 

"The Road to Gate-All-Around and Its Impact on Analog Design"

Date/Time: 

11 Sep 2025 04:00 PM CEST to 06:30 PM CEST

Location: 

Schatzbogen 7; Munich, Bayern, Germany 81829

Building: NXP Semiconductors Germany GmbH

Host:

Germany Section Chapter, SSC37

Co-sponsored by NXP Semiconductors

Contact:

Event Host

FREE REGISTRATION 

Abstract: Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around transistor architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. We will then shift to summarize the challenges that CMOS technology scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design closure, we will cover design strategies on how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling, including the migration to heterogeneous integration as prophesied by Gordon Moore's seminal 1965 paper.

Biography: Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel's Angstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received a B.A.Sc. in engineering physics from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford. After several years in CMOS process integration, Alvin has since worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary, SSCS Global Chapters Chair, and again as Distinguished Lecturer. Alvin has authored over 70 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. He holds 29 US patents and recently received the ISSCC 2024 Outstanding Forum Speaker Award.

[paper] An Open-Source AMS Circuit Optimization

Z. Li and A. Chan Carusone

An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning: 

From Specifications to Layouts

in IEEE Access, vol. 12, pp. 150032-150045 (2024) 

DOI: 10.1109/ACCESS.2024.3478832

Abstract: This paper presents a fully open-sourced AMS integrated circuit optimization framework based on reinforcement learning (RL). Specifically, given a certain circuit topology and target specifications, this framework optimizes the circuit in both schematic and post-layout phases. We propose using the heterogeneous graph neural network as the function approximator for RL. Optimization results suggest that it can achieve higher reward values with fewer iterations than the homogeneous graph neural networks. We demonstrate the applications of transfer learning (TL) in optimizing circuits in a different technology node. Furthermore, we show that by transferring the knowledge of schematic-level optimization, the trained RL agent can optimize the post-layout performance more efficiently than optimizing post-layout performance from scratch. To showcase the workflow of our approach, we extended our prior work to optimize latched comparators in the SKY130 and GF180MCU processes. Simulation results demonstrate that our framework can satisfy various target specifications and generate LVS/DRC clean circuit layouts.

FIG: Proposed AMS IC optimizer overview. 

The picture is adapted from [Z. Li and A. C. Carusone; 2023]

Acknowledgment: The authors would like to thank Dr. Hossein Shakiba from Huawei Technologies
for his valuable discussions throughout this project.

[REF] Z. Li and A. C. Carusone, "Design and optimization of low-dropout voltage regulator using relational graph neural network and reinforcement learning in open-source SKY130 process," in Proc. IEEE/ACM Int. Conf. Comput. Aided Design (ICCAD), Oct. 2023, pp. 1–9.