[mos-ak] [Announcement] MOS-AK INAOE Workshop, Puebla (MX), May 14-16, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

MOS-AK INAOE Workshop

Puebla (MX), May 14-16, 2025

The semiconductor industry is crucial for Mexico's development, and it is the key for the future growth of the country economics. Producing advanced integrated circuits involves many steps, beginning with the idea for the circuits, technology, IC design and its simulation, layout generation, manufacturing and functional tests, among them. All of these stages require dedicated, specialized software programs, generally very expensive, which makes them onerous for the majority of academic institutions in the country. Recently, however, there has been an important effort in developing free open source tools for this purpose, and thus accessible to any educational institutions. These include open source tools spanning from the design to the fabrication of the circuits.  In these initial stages, having these tools available aims at fostering research and education in the field of prototyping IC design, without considering manufacturing in large quantities.

The mail goal of MOS-AK INAOE workshop is to expound on the available free open source tools for each IC development step in the design, simulation and manufacturing of integrated circuits, as well as presenting the options for the fabrication of ICs.

It is very important to train people, build the semi workforce with the basic knowledge needed to grow the semiconductor industry in Mexico. Professionals, including international researchers and experts from INAOE and other institutions, will give talks and courses to explain the tools, their potential uses, showing the engineering requirements and IC design applications.

 

The MOS-AK workshop program will be published online:

<https://mos-ak.org/puebla_2025/>

Space is limited, so we invite you to register at the following link:

<https://www-elec.inaoep.mx/~taller_semiconductores/registro.php>

-- R.Murphy and W.Grabinski 

-- on the behalf of the MOS-AK INAOE Organizing Committee

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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WG230425

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[C4P] ICEE 2025

7th International Conference on Emerging Electronics (ICEE 2025)

Hilton Embassy Manyata Business Park, Bengaluru (IN)

December 13-16, 2025

Upcoming ICEE 2025 is a flagship IEEE EDS four-day conference, organized to foster cutting-edge discussions and collaborations in semiconductor technologies. ICEE 2025 will feature a diverse range of sessions, including, Technical and rump sessions, Industry-academia discussions, Plenary talks by distinguished experts, Policy sessions on the future of semiconductor technologies.

ICEE 2025 invites papers (4 page Abstract submission deadline: Aug.25 2025) on a diverse and comprehensive range of topics that span materials, processes, devices, circuits, systems, modeling, and reliability. This program is curated by an international team of academic and industry leaders. This edition of ICEE is especially important, given the ambitions of major global economies (such as USA, EU, Japan, India, etc.) in semiconductor manufacturing. This focus is reflected in the composition of ICEE's technical program and organizing committee, with top industry leaders on board. ICEE'25 edition plans to offer 3 Plenary Talks, 5 Keynote Talks, 150+ Invited and Platform/Oral Talks, 100+ Posters, Tutorial Sessions, Evening Industry Sessions, and Industry Exhibits with 800+ International Audiences and Industry Participation. The conference will offer opportunities to contribute, network, learn, collaborate and grow in the areas listed below. For the contributed papers, please find below the call for paper, ICEE themes/tracks, submission guidelines and 4-page abstract templates. In case of questions, please feel free to write to us at secretary@ieee-icee.org. Please keep checking the website and our social media handles for new updates [read more]

[paper] Ferroelectric MOSFET

Jean-Michel Sallese and Vincent Meyer

The Ferroelectric MOSFET: A Self-Consistent Quasi-Static Model and its Implications

IEEE transactions on electron devices 51, no. 12 (2004): 2145-2153

DOI: 10.1109/TED.2004.839113

Abstract: We report a new approach to modeling the metal-ferroelectric-insulator field-effect transistor (MFIS-FET) that leads to a physical understanding of the device in quasi-static operation. Compared to previous works, the local state of the ferroelectric layer is calculated self-consistently along the channel, without assuming any predefined hysteresis path. Further, this approach gives a consistent description of the MFIS-FET in all regions of operation, and predicts the unexpected situation where both inversion and accumulation coexist in the channel. When external voltages are varied simultaneously, we show that both current and polarizations are sensitive to the correlation between the gate, source, and drain potentials. Finally, basic derivation of analytical relations for overall MFIS-FET optimization is discussed.

Fig: Schematic description of the ferroelectric MOSFET and evolution of the ferroelectric polarization along the channel as function of the gate voltage when the device operates at low VDS (in linear mode). The progression of the gate potential is indicated by the arrows. The ferroelectric saturated loop is also plotted for clarity (dash-dotted).

Acknowledgment: The authors would like to thank C. McAndrew for his constructive comments on the manuscript.

[paper] Generative AI for Analog IC Design

D. Noori Zadeh and M. B. Elamien

Generative AI for Analog Integrated Circuit Design: Methodologies and Applications

in IEEE Access, vol. 13, pp. 58043-58059, 2025

DOI:10.1109/ACCESS.2025.3553743. 

* Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON, Canada

Abstract: Electronic Design Automation (EDA) in analog Integrated Circuits (ICs) has been the focus of extensive research; however, unlike its digital counterpart, it has not achieved widespread adoption. In this systematic review, we discuss recent contributions in the last five years, highlighting methods that address data scarcity, topology exploration, process-voltage-temperature (PVT) variations, and layout parasitics. Our goal is to support researchers new to this domain by creating a comprehensive collection of references and practical application guidelines. We provide a methodological review of state-of-the-art machine learning (ML) approaches, including graph neural networks (GNNs), large language models (LLMs), and variational autoencoders (VAEs), which have been successfully applied to analog circuit sizing tasks. To the best of authors' knowledge, this is the first review to comprehensively explore the application of generative AI models in analog IC circuit design. We conclude that future research could focus on few-shot learning with domain-adaptation training of generative AI methods to simplify the design tasks such as human-tool interaction or guided design space exploration.

FIG.1: Analog design automation flow, focusing on circuit-level automation.

Acknowledgements: This work was supported by the Natural Sciences and Engineering Research Council (NSERC) of Canada through its Discovery Grant (DG) Program under Grant RGPIN-2024-06826.

[paper] SEMIDV Device Simulator with Quantum Effects

Chien-Ting Tung

SEMIDV: A Compact Semiconductor Device Simulator with Quantum Effects

ArXiv preprint arXiv:2504.00214 (2025)

Abstract: In this paper, I present SEMIDV – a compact semiconductor device simulator incorporating quantum effects. SEMIDV solves the Poisson-Drift-Diffusion equations for semiconductor devices and provides a user-friendly Python interface for scripting and data analysis. Localization landscape theory is introduced to provide quantum corrections to the Drift- Diffusion equation. This theory directly solves the ground state of the Schrödinger equation without further approximation, offering an efficient solution for quantum effect modeling. Additionally, a compact mobility model considering ballistic transport is developed to capture the ballistic length dependence of mobility and the velocity overshoot effect in short-channel devices. Finally, a study on a nanosheet FET using SEMIDV is conducted. I analyze the electrical characteristics of a state-of- the-art GAA/RibbonFET with a 6 nm gate length and discuss the effects of velocity overshoot and quantum confinement on currents and capacitances. A design for an ultra-short-channel transistor with a gate length down to 4.5 nm with a Vdd = 0.45 V is proposed to push the boundaries of integrated circuit technology further.

FIG: Silicon 6nm RibbonFET CMOS structure for SIMIDV calibration