[book] Microelectronic Circuits

Sedra, Adel S., Smith, Kenneth Carless, Carusone, 

Tony Chan, Gaudet, Vincent. 

Microelectronic Circuits. 

United Kingdom: Oxford University Press, 2020

Circuits by Sedra and Smith has served generations of electrical and computer engineering students as the best and most widely-used text for this required course. Respected equally as a textbook and reference, "Sedra/Smith" combines a thorough presentation of fundamentals with an introduction to present-day IC technology. It remains the best text for helping students progress from circuit analysis to circuit design, developing design skills and insights that are essential to successful practice in the field. Significantly revised with the input of two new coauthors, slimmed down, and updated with the latest innovations, Microelectronic Circuits, Eighth Edition, remains the gold standard in providing the most comprehensive, flexible, accurate, and design-oriented treatment of electronic circuits available today.

Appendix

• B. SPICE Device Models and Design with Simulation Examples

Model files for representative CMOS technologies are provided below:

• 0.8 um CMOS
• 0.35 um CMOS
• 0.18 um CMOS
• 45 nm CMOS
• 7nm FinFET

 

[paper] Sub-THz HICUM for SiGe HBTs

Soumya Ranjan Panda, Thomas Zimmer, Anjan Chakravorty, Nicolas Derrier

and Sebastien Fregonese

Exploring Compact Modeling of SiGe HBTs in Sub-THz Range With HICUM

in IEEE TED, DOI: 10.1109/TED.2023.3321017.

IMS laboratory, CNRS, University of Bordeaux (F)
Department of Electrical Engineering, IIT Madras (IN)
STMicroelectronics, 38920 Crolles (F)

Abstract : This study delves deeper into the high frequency (HF) behavior of state-of-the-art sub-THz silicon germanium heterojunction bipolar transistors (SiGe HBTs) fabricated with 55 nm BiCMOS process technology from STM. Using measurement data, calibrated TCAD simulations, and compact model simulations, we present a comprehensive methodology for extracting several HF parameters (related to parasitic capacitance partitioning and nonquasi-static effects) of the industry standard model, HICUM. The parameter extraction strategies involve thorough physics-based investigation and sensitivity analysis. The latter allowed us to precisely evaluate the effects of parameter variations on frequency dependent characteristics. The accuracy of the finally deployed model is tested by comparing the model simulation with measured small-signal two-port parameters of SiGe HBTs up to 330 GHz.

FIG: a.)  TEM image of the SiGe HBT device; b.) 2D TCAD structure simulation; c.) Large signal equivalent circuit of HICUM L2 compact model; d.) and e.) adjunct networks for vertical NQS effects

Acknowledgment: The authors would like to acknowledge Dider Celi, STM, for valuable discussion about the compact modeling of heterojunction bipolar transistors (HBTs), and they also like to thank STM for providing the silicon wafers. This work was supported by NANO2022 Important Project of Common European Interest Project (IPCEI), and SHIFT Grant ID 101096256.

[paper] Lorentzian noise spectra in compact models

Nikolaos Makris*†, Loukas Chevas* and Matthias Bucher*

Verilog-A based implementation of Lorentzian noise spectra in compact models

26th International Conference on Noise and Fluctuations - ICNF

17th-20th October 2023 - Grenoble - France

DOI: 10.1109/ICNF57520.2023.10472771

* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece        European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece

Abstract:In this paper, a simple Verilog-A implementation of Lorentzian noise spectra is introduced that can be used in compact models for the frequency-domain simulation of low-frequency noise in electronic devices. For this purpose, a thermal noise source is combined with a low-pass filter as realized using laplace_nd Verilog-A function in order to achieve Lorentzian noise behavior. This modeling approach can be implemented in any Verilog-A compact model and provides the means for bias-dependent Lorentzian trap modeling. This approach is evaluated in commercial simulator. Application examples are provided to demonstrate the capabilities of this approach.

FIG: Bias dependent model implemented in the EKV3 MOSFET model

Acknowledgements: This work was co-funded by the ERASMUS+ Programme of the European Union (Contract number: 101004049 - EURECA-PRO - EAC-A02-2019 / EAC-A02-2019-1). This research has been co-financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH - CREATE - INNOVATE (project code: T2EDK-00340).

[mos-ak] [2nd Announcement] 16th International MOS-AK Workshop Silicon Valley, Dec. 13, 2023

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

16th International MOS-AK Workshop

Silicon Valley, December 13, 2023

2nd Announcement and C4P

The 16th International MOS-AK Workshop on Compact/SPICE Modeling will take place on Dec.13, 2023, in timeframe of IEDM and Q4 CMC Meetings. This event is coorganized by Keysight Technologies, our local host and partner, and the Extended MOS-AK TPC Committee. We invite you to join us for MOS-AK workshop and learn from the experts in the field of SPICE/Verilog-A modeling.

Planned 16th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Device level modeling for Agroelectronics, Bio/Med, IoT applications
• Device cryogenic operation for Quantum Computing 
  
• Nanoscale semiconductor devices/circuits and its reliability/ageing
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies, Open Access PDK(eg: Skywater 130nm CMOS, IHP 130nm RF BiCMOS) 

Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Free Registration is open (any related enquiries can be sent to registration@mos-ak.org)

Important Dates: 

• 2nd Announcement: Oct. 20213
  
• Final Workshop Program: Nov.28 2023
• MOS-AK Workshop: Dec.13, 2023
  in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski for Extended MOS-AK Committee

WG171023

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[Call for Book Chapters] Perovskite Solar Cells

Call for Book Chapters:

Book Title: Perovskite Solar Cell

Table of Content

• Introduction to Perovskite Solar Cells
• Fundamentals of Perovskite Materials
• Fabrication Techniques
• Characterization Methods
• Perovskite Solar Cell Physics

Important Dates:

Chapter proposal submission deadline: 15th November 2023
Notification of Acceptance: 21st November 2023
Full Chapter submission: 30th January 2024
Acceptance/Rejection Notification: 10th February 2024

Prospective authors are requested to submit their chapter proposals/full chapters. 

<https://www.routledge.com/our-customers/authors/publishing-guidelines>

There are no publication fees for a chapter submitted to this book publication. All submitted chapters will be peer reviewed. For chapter proposals/full chapter submission and queries: tdsubash2007@gmail.com