[C4P] IJNM - 7th Sino MOS-AK Workshop

Call for Papers

Special issue on the 7th International Sino MOS-AK Workshop

Submission deadline: Sunday, 31 December 2023

The 7th International Sino MOS-AK Workshop was held on 11-13th August 2023 in Nanjing, China. MOS-AK working group has more than 20 years enabling  compact modeling  R&D exchange. For additional detailed info, please refer to MOS-AK website:
http://www.mos-ak.org/nanjing_2023/.

With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. With this background, the workshop aims to strengthen a network and discussion forum among experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of Analytical Modeling, Compact Modeling, Characterization and Simulation techniques for advanced devices, circuits and technologies. Modeling and validation technique of all solid-state devices, including, Si, III-V, power, nanoscale electronic structures and other related new devices are within the scope of the conference. The theme of MOS-AK is "Bridge of Process Technology and Integrated Circuits & Systems Design".

Topics for this call for papers include but not restricted to:

• Advances in semiconductor technologies and processing (CMOS, SOI, FINFET, III-V, Wide band-gap)
• CM of passive active, sensors, and actuators
• Emerging Devices, photonic devices, CMOS, and SOI-based memory cell
• RF/THz device and Power device modeling
• Power device and Power integration
• Reliability modeling
• AI and machine learning in EDA & modeling application
• Nanoscale CMOS devices and circuits
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open-source TCAD/EDA modeling and simulation
• Technology R&D, DFY, DFT and IC Designs
• Chiplet Modeling and Packaging-related modeling
• Foundry/Fabless Interface Strategies, Open Access PDKs
• DTCO & STCO-related EDA tools/technologies
• Other related topics

Guest Editors:

• Jun Zhang
  Nanjing University of Posts and Telecommunications (CN)
• Yuehang Xu
  University of Electronic Science and Technology of China (CN)
• Wladek Grabinski
  MOS-AK (EU)

Submission Guidelines/Instructions

Authors of papers presented at the conference will be invited to submit an extended paper by 31 December 2023 to a special issue of IJNM. Manuscripts for this special issue should adhere to the requirements for regular papers in IJNM as specified in the journal’s Author Guidelines. The manuscripts will be submitted via the IJNM manuscript submission site, https://wiley.atyponrex.com/journal/jnm. Authors must choose the special issue title from the dropdown list on the “Additional Information” tab.

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[book chapters] Equation-Based Compact Modeling

 

Debnath, P., Sarkar, B., & Chanda, M. (Eds.). (2023).

Differential Equation Based Solutions 

for Emerging Real-Time Problems

(1st ed.). CRC Press 

DOI 10.1201/9781003227847

Chapter: Differential Equation-Based Compact 2-D Modeling of Asymmetric Gate Oxide Heterojunction Tunnel FET; By: Sudipta Ghosh, Arghyadeep Sarkar

Abstract: Tunnel Field Effect Transistor (TFET) has emerged as an effective alternative device to replace MOSFET for a few decades. The major drawbacks of MOSFET devices are the short-channel effects, due to which the leakage current increases with a decrease in device dimension. So, scaling down TFET is more efficacious than that of MOSFETs. Sub-threshold swing (SS) is another advantageous characteristic of TFET devices for high-speed digital applications. In TFETs the SS could be well below 60 mV/decade, which is the thermal limit for MOSFET devices and therefore makes it more suitable than MOSFET for faster switching applications. It is observed from the literature studies that the performances of the TFET devices have been explored thoroughly by using 2-D TCAD simulation but an analytical model is always essential to understand the physical behavior of the device and the physics behind this; which facilitates further, the analysis of the device performances at circuit level as and when implemented.

Chapter: Differential Equation-Based Analytical Modeling of the Characteristics Parameters of the Junctionless MOSFET-Based Label-Free Biosensors; by: Manash Chanda, Papiya Debnath, Avtar Singh

Abstract: Recently Field Effect transistor (FET)-based biosensing applications have gained significant attention due to the demand for quick and accurate diagnosis of different enzymes, proteins, DNA, viruses, etc; cost-effective fabrication process; portability and better sensitivity and selectivity compared to the existing biosensors. FET is basically a three-terminal device with source, drain, and gate terminals. Basically, the gate terminal controls the current flow between the source and drain terminals. In FETs, first, a nanogap is created in the oxide layer or in the gate by etching adequate materials. When the biomolecules are trapped inside the nanocavity then the surface potentials change and also the threshold voltage varies. As a result, the output current also changes. Finally, by measuring the changes in the threshold voltage or the device current, one can easily detect the biomolecules easily.

[open positions] TU Warsaw

 

We [TU Warsaw] offer two #openpositions for PhDs who perform research in the broad field of technology, characterization, and modeling of #semiconductor structures and devices. The first position is for a #postdoctoralfellowship, while the second one is for an #assistantprofessor. The specifics of both offers are attached to this post. The candidates will be employed in the Institute of Microelectronics and Optoelectronics, Faculty of Electronics and Information Technologies of Warsaw University of Technology. Both positions will start in December 2023/January 2024.

Links to offers with a list of documents to apply:

• (PostDoc): https://lnkd.in/di7dwV5p
• (Assistant Professor): https://lnkd.in/dk5d6Dfa

Interested applicants should contact Robert Mroczyński with a complete professional CV (including educational background, experience, and a list of publications), an electronic version (pdf) of the Ph.D. thesis, and the contact information to at least two experts who would provide letters of recommendation.

[Short Course] MACHINE LEARNING FOR ELECTRON DEVICES

Short Course on

MACHINE LEARNING FOR ELECTRON DEVICES

3-6 October 2023, IIT Roorkee

Four day residential program to learn and explore the role of Machine Learning in shaping the future of the semiconductor EDA.

KEY HIGHLIGHTS

• Lectures from basic machine learning to advanced ideas
• Hands-on tutorials for developing your own Machine learning models
• Excellent networking opportunity
• Interaction with experts from industry and academia
• UG Fellowships up to ₹ 10000/month for selected participants
• Funding opportunity upto INR 40Lacs as start-up seed grant for selected ideas

EVENT SCHEDULE <http://ece.iitr.ac.in/diraclab/mled23/>

[paper] GaN-on-Si HEMT

Rijo Baby^a, Manish Mandal^b, Shamibrota K. Roy^b, Abheek Bardhan^a, Rangarajan Muralidharan^a, Kaushik Basu^b, Srinivasan Raghavan^a, Digbijoy N. Nath^a

8A, 200V normally-off cascode GaN-on-Si HEMT: From epitaxy to double pulse testing

Microelectronic Engineering, Volume 282, 2023, 112085,

DOI: 10.1016/j.mee.2023.112085.

a Center for Nanoscience and Engineering (CeNSE), (IISc Bangalore (IN)
b Department of Electrical Engineering, IISc Bangalore (IN)

Abstract: In this paper, we provide a comprehensive study on all aspects of development of normally-off multi-finger III-nitride HEMT on Silicon in cascode configuration. AlGaN/GaN HEMT epi-stack with in situ SiN cap was grown on 2" Silicon (111) using MOCVD, utilizing a 2-step AlN nucleation, step-graded AlGaN transition layer and C-doped GaN buffer. Depletion-mode HEMTs in winding gate geometry with a gate width of 30mm were fabricated with thick electroplated metal contacts and an optimized bilayer SiN passivation. Devices were diced and packaged in TO254 with conducting epoxy and Au-coated ceramic substrate. These packaged D-mode HEMTs exhibited a threshold voltage (Vth) of −12V, maximum ON current of 10A and a 3-terminal hard breakdown in excess of 400V. Bare dies of D-mode HEMTs were then integrated with commercially procured silicon MOSFET in a TO254 package in cascode configuration to achieve Vth>2V, ON current of 8Aand breakdown >200V. The normally-off cascaded GaN HEMTs were subjected to various gate and drain stress measurements and were found to exhibit a Vth shift of 10 mV after 1000 s of positive gate (+5V) stress. The input and output capacitances of the cascode devices were measured to be 1 nF and 0.8 nF, respectively. The 3rd quadrant operation was checked at 8 A on-state current level to reveal a lower voltage drop of 0. V. Finally, cascode HEMTs were subjected to double pulsed testing (DPT) using a half-bridge evaluation board. On and off rise times of 52 ns and 59 ns were obtained along with energy loss of 25 μJ and 20 μJ, respectively, for devices switched at 8A,100V.

FIG: 8A, 200 V normally-off cascode GaN-on-Si HEMT

Acknowledgement: This research was supported by ISRO/SCL. We also acknowledge funding support from MHRD through the NIEIN project, from MeitY and DST Nano Mission through NNetRA. We thank the Micro and Nano Characterization Facility (MNCF) staff and facility technologists of the National Nano Fabrication Facility (NNFC). We thank Anirudh Venugopalarao, Parimalazhagan Serralan, Mr. Veera Pandi N, Dr. M.M Nayak, Mr. Malingu G and Bharath Kumar M for their support.