[paper] Organic Semiconductor Devices

D. Oussalah^1,2, R. Clerc², J. Baylet¹, R. Paquet¹, C. Sésé¹, C. Laugier¹, B. Racine¹

and J. Vaillant¹

On the minimum thickness of doped electron/hole transport layers 

in organic semiconductor devices 

Journal of Applied Physics 130, 125502 (2021);

DOI: 10.1063/5.0060429

  
1Université Grenoble Alpes, CEA, Leti, Grenoble 38000, France
2Université de Lyon, UJM-Saint-Etienne, CNRS, IOGS, Lab. Hubert Curien, UMR5516 St-Etienne, France

  

Abstract: Doped hole (respectively electron) transport layers [HTLs (respectively ETLs)] are commonly used in evaporated organic devices to achieve high work function hole contact (respectively low work function electron contact) in organic LEDs to inject large current, in solar cells to increase the open circuit voltage, and in photodetectors to minimize the dark current. However, optimization of the HTL thickness results from a delicate trade-off. Indeed, on the one hand, to minimize the impact of HTLs on light propagation and series resistance effects, it is commonly admitted that HTLs must be kept as thin as possible. In this work, a model, validated by drift and diffusion simulations, has shown that, depending of the doping level, a minimum thickness between 10 and 20 nm was needed to prevent the transport layer work function from degradation due to field effects. Experiments have been performed on template p-only devices featuring a single HTL of various thicknesses and doping, confirming the validity of the model. Finally, simulations have been performed on a p-i-n device featuring both HTL and ETL. These results constitute precious indications for the design of efficient evaporated organic LEDs, solar cells, or photodetectors.

Fig: Image of a top view of the 200 mm silicon wafer processed to realize TiN/STTB:F4TCNQ/ZnPc:C60/Ag devices.

[paper] Enhancing multi-functionality of reconfigurable transistors

Y.V. Bhuvaneshwari and Abhinav Kranti

Enhancing multi-functionality of reconfigurable transistors 

by implementing high retention capacitorless dynamic memory

Semicond. Sci. Technol. 36 (2021) 115003 (9pp)

DOI:10.1088/1361-6641/ac2315

Low Power Nanoelectronics Research Group, Department of Electrical Engineering, Indian Institute of Technology Indore, Simrol, Indore 453552, Madhya Pradesh, India

Abstract: A key indicator of multi-functional attributes of a transistor is technological competitiveness vis-a-vis existing architectures. Apart from the well-known logic circuit implementation through reconfigurable field effect transistors (RFETs), this work showcases feasible memory operation by realising capacitorless (1T) dynamic random access memory (DRAM). The memory operation in RFET is achieved through back control gate which creates an electrostatic potential well to store holes. Due to the inherent features of RFET architecture a wider and deeper potential well results in a significantly high retention time (RT) of 2.3s at 85C for a total length of 90 nm. Apart from high retention, RFET based 1T-DRAM exhibits a low write time of ∼2ns, sense margin (SM) of ∼76µA/µm and a high current ratio (CR) of ∼105. Benchmarking the performance metrics against previously published results indicates competitiveness for RT in terms of total length, storage volume and high temperature operation. Critical insights aiding competitive multi-functional behaviour through 1T-DRAM highlights the possible implementation of logic and memory blocks with RFETs.

Fig: Schematic diagram of a planar DG RFET with two PGs and one CG. The CG length (Lcg) and PG length (Lpg) were varied from 100 to 10 nm, spacing (Lgap) between CG and PG was varied from 40 to 30 nm, and the undoped film of thickness (Tsi) was varied from 9 to 12 nm. The thickness of HfO2 layer (THfO2) was kept constant at 4 nm. A midgap workfunction (φm=4.7 eV) was used for polarity and CGs. Holes are stored at the back surface (y=Tsi) in the potential well created due to the application of a negative voltage at the back CG.

Acknowledgments: This work was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Government of India, under GrantCRG/2019/002937.

[@iannak1] The size of the investment needed for one single new state-of-art fab is way beyond the Semiconductor Industry support plans of all European governments #semi #fab #chip #wafer #investment #EU https://t.co/aj6fnXB4r8

[@iannak1] The size of the investment needed for one single new state-of-art fab is way beyond the Semiconductor Industry support plans of all European governments #semi #fab #chip #wafer #investment #EU https://t.co/aj6fnXB4r8

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October 01, 2021 at 08:55AM
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[SEMI Press Release] SEMI Applauds European Chips Act, Aimed at Boosting Semiconductor R&D and Manufacturing https://t.co/WZOd8Sw5Sh #Europe #research #development #semiconductors #manufacturing #publicpolicy #semi #chip #EU https://t.co/mHGUZkRaXY

[SEMI Press Release] SEMI Applauds European Chips Act, Aimed at Boosting Semiconductor R&D and Manufacturing https://t.co/WZOd8Sw5Sh #Europe #research #development #semiconductors  #manufacturing #publicpolicy #semi #chip #EU https://t.co/mHGUZkRaXY

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[paper] New Design Concept for the IoT Era

Pedro Toledo, Graduate Student Member, IEEE, Roberto Rubino, Graduate Student Member, IEEE, Francesco Musolino, Member, IEEE, and Paolo Crovetti, Senior Member, IEEE

Re-Thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

IEEE Transactions on Circuits and Systems—II: Express Briefs, 

Vol. 68, No. 3, March 2021

DOI:  10.1109/TCSII.2021.3049680

* DET, Politecnico di Torino (IT)

Abstract: A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.

Fig: a) Kuijk’s Bandgap voltage reference [i]. b) Microcontroller-based proof

of concept prototype.

REF:

[i] K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-StateCircuits, vol. SSC-8, no. 3, pp. 222–226, Jun. 1973.