[paper] Dynamic Simulation of a-IGZO TFT Circuits Using AFCM

Y. Hernández-Barrios¹, J. N. Gaspar-Angeles¹, M. Estrada¹, B. Íñiguez², And A. Cerdeira¹

Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

IEEE Journal of the Electron Devices Society, vol. 9, pp. 464-468, 2021, 

doi: 10.1109/JEDS.2020.3045347

1 SEES, Departamento de Ingeniería Eléctrica, CINVESTAV-IPN, Mexico City 07360, Mexico
2 Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, URV, Tarragona 43007, Spain

Abstract: The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.

FIG: Fabricated and measured 19-stages Ring Oscillator (RO)

of amorphous oxide semiconductors (AOS) thin film transistors (TFTs) 

Aknowlwgement: This work was supported in part by the Consejo Nacional de Ciencia y Tecnología (CONACYT) under Project 237213 and Project 236887; in part by the H2020 program of the European Union under Contract 645760 (DOMINO); in part by contract “Thin Oxide TFT SPICE Model” with Silvaco Inc., under Grant T12129S; and in part by ICREA Academia 2013 from ICREA Institute and the Spanish Ministry of Economy and Competitiveness under Project TEC2015-67883-R GREENSENSE.

 

[paper] Does the Threshold Voltage Extraction Method Affect Device Variability?

Gabriel Espiñeira; Antonio J. García-Loureiro; Natalia Seoane

Does the Threshold Voltage Extraction Method Affect Device Variability?

IEEE J-EDS, vol. 9, pp. 469-475, 2021,

DOI 10.1109/JEDS.2020.3046122.

* CITIUS, Universidade de Santiago de Compostela, Galicia, Spain

Abstract: The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( VTH ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in VTH and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the VTH distribution ( σVTH ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the VTH extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

FIG: General capabilities of the FoMPy library [1]. FoMPy is able to import your data into a dataset, and after optional conditioning (data filtering or interpolation) is able to extract and plot some of the most commonly studied FoMs.

This work was supported in part by the Spanish Government under Grant PID2019-104834GB-100 and Grant RYC-2017-23312, and in part by the Xunta de Galicia and FEDER (accreditation 2016–2019) under Grant GRC 2014/008, Grant ED431G/08, and Grant ED431F-2020/008.

REF:

[1] FoMpy: A figure of merit extraction tool for semiconductor device simulations <https://github.com/gabrielesp/FoMpy>

[2] VENDES. A.J.Garcia-Loureiro, N.Seoane, M.Aldegunde, R.Valin, A.Asenov, A.Martinez and K.Kalna “Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, June 2011 doi=10.1109/TCAD.2011.2107990

[3] G.Espiñeira, N.Seoane, D.Nagy, G.Indalecio and A.J.García Loureiro, “FoMPy: A figure of merit extraction tool for semiconductor device simulations” in 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) doi:10.1109/ULIS.2018.8354752

[4] G.Espiñeira, D.Nagy, G.Indalecio, A.J.García Loureiro and N.Seoane, “Impact of threshold voltage extraction methods on semiconductor device variability” Solid-State Electronics, Volume 159, 2019, Pages 165-170, https://doi.org/10.1016/j.sse.2019.03.055

[PhD] VLSI Interconnect Reliability

Shaoyi Peng

Modeling and Simulation Methods for VLSI Interconnect Reliability Focusing 

on Time Dependent Dielectric Breakdown

PhD Dissertation in Electrical Engineering

University of California Riverside

https://escholarship.org/uc/item/966241xk (March 2021)

Abstract: Time dependent dielectric breakdown (TDDB) is one of the important failure mechanisms for Copper (Cu) interconnects that are used in VLSI circuits. This reliability effect becomes more severe as the space between wires is shrinking and low-k dielectric materials (low electrical and mechanical strength) are used. There are many studies and theories focusing on the physics of it. However, there is limited research from the electronics design automation (EDA) perspective on this topic, aiming to evaluate, or alleviate it from the perspective of designing a VLSI chip. This thesis compiles several studies into evaluating TDDB on the circuit level, and engineering methods that help the evaluation. The first work extends the study of a published physics model on simplified yet practical cases. It simplifies the calculation of lifetime by deriving an analytic solution and applying fitting methods. The second study proposes a new way to evaluate lifetime of a chip by extending the models of simple interconnect structures to the complete chip. This method is more robust as it focuses more on a complete chip. However, heavy dependence of finite element method (FEM) makes the flow very slow. The third study adopts machine learning methods to accelerate this slow evaluation process. The proposed method is also applicable to other similar electrostatics applications. Last but not least, the fourth study focuses on a GPU based LU factorization algorithm, which, on a broader aspect, is a universal numerical algorithm used in many different simulation applications, which can be helpful to TDDB evaluations as it can be used in FEM.

Fig: Structure of two copper interconnect wires and the IMD in the cross-section SEM image after TDDB failure [sem]

REF: 

[sem] N. Suzumura, S. Yamamoto, D. Kodama, K. Makabe, J. Komori, E. Murakami, S. Maegawa, and K Kubota. A new TDDB degradation model based on Cu ion drift in Cu interconnect dielectrics. In IEEE Int. Reliability Physics Symposium (IRPS), pages 26–30, 2006.

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