#Flying on #Mars fueled with #opensource software

#Flying on #Mars fueled with #opensource software | ZDNet https://t.co/t8K6REnpdO #semi pic.twitter.com/2ttgq3v9A4

— Wladek Grabinski (@wladek60) April 20, 2021

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April 20, 2021 at 11:56PM
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[papers] Compact Modeling

[1] Nicolo Zagni; Simulation and Modeling Methods for Predicting Performance and Reliability Limits of 21st-Century Electronics; PhD Thesis, Universita Degli Estudi Di Modena e Reggio Emilia; Anno Accademico 2019–2020 (CICLO XXXIII)

Abstract: In recent years, a plethora of novel semiconductor devices have started emerging as worthy heirs of Silicon-based transistors – giving rise to the ’post-Moore’ era. Traditional electronics is mostly based on Si devices, – from logic to memory, to high frequency/power and sensing applications – but this paradigm is changing thanks to the developments in different fields ranging from physics and semiconductor materials, to processing techniques and computing architectures. In this hectic new scenario, before even considering a new technology as a replacement of the existing ones, the limiting factors to its performance and reliability need to be well-understood and engineered for. In this sense, simulations and physics-based modeling represent critical tools to make sure that newly conceived technologies stand up to the requirements of 21st century electronics. In this thesis, state-of-the-art simulation and compact modeling tools are exploited to analyze the performance and reliability limits of several emerging technologies. Specifically, this dissertation is focused on four application scenarios and the relative candidate technologies that aim to providing enhanced performance/reliability compared to Si-based counterparts. These are: i) III-V MOSFETs for logic/digital circuits, ii) resistive-RAMs and ferroelectric-FETs for non-volatile memory and in-memory computing, iii) GaN-based high-speed transistors for power applications, and iv) negative capacitance transistors for biosensing.

Fig: Energy bandgap (Eg) vs lattice constant (a) of different semiconductor materials, showing that In0.57Ga0.43As has the same lattice constant as InP. Adapted from: https://www.iue.tuwien.ac.at/phd/brech/diss.htm (visited on 12/20/2020).

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[2] G. Maroli, A. Fontana, S. M. Pazos, F. Palumbo and P. Julián, "A Geometric Modeling Approach for Flexible, Printed Square Planar Inductors under Stretch," 2021 Argentine Conference on Electronics (CAE), Bahia Blanca, Argentina, 2021, pp. 61-66, DOI: 10.1109/CAE51562.2021.9397568.

Abstract: In this work a compact model for square planar inductors printed on flexible substrate is proposed. The approach considers the deformation of the metal traces of square spiral inductors when the substrate is subjected to physical stretch. The model considers a typical pi-network for the device, where each component is calculated for different stretching values adapting widely accepted models on the literature for the total inductance, the AC resistance and the ground coupling and inter-wounding capacitances. Model results are contrasted to 3D full electromagnetic wave simulations under parametric sweeps of the dimensions calculated under stretch. Results show good agreement within a 20 % stretch up to the first resonance frequency of the structure. The model can prove useful for the optimization of component design for printed applications on flexible substrates.

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[3] H. Kikuchihara et al., "Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching," 2021 International Symposium on Devices, Circuits and Systems (ISDCS), Higashihiroshima, Japan, 2021, pp. 1-4, DOI: 10.1109/ISDCS52006.2021.9397904.

Abstract: Demands for higher-voltage MOSFET application are increasing, for which a Super-Junction MOSFET, sustaining the voltages in the range of 500V, has been developed based on the trench-type structure. Due to the huge bias applied, a new leakage-current type is induced during switching, which causes a switching-power-loss increase. Creating a compact model for circuit design, which includes this additional leakage current, is the purpose of the present development. The model describes the depletion-width variation, caused during the switching-on of the device, with the use of the internal node potential, determined accurately by iteration. It is verified, that the new compact model can accurately predict the device performances for different device structures. This capability can be used for device optimization to realize low-power circuitry.

Foundry Wars Begin

Foundry Wars Begin [Mark LaPedus https://t.co/w4Z02tvMPq] #semi pic.twitter.com/x0NKvekgI0

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April 19, 2021 at 11:59PM
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[paper] Deep-Learning Assisted Compact Modeling

Hei Kam

Deep-Learning Assisted Compact Modeling of Nanoscale Transistor

CS230 Deep Learning; Stanford University (2021)

Abstract - Transistors are the basic building blocks for all electronics. Accurate prediction of their current-voltage (IV) characteristics enables circuit simulations before the expensive silicon tape-out. In this work, we propose using deep neural network to improve the accuracy for the conventional, physics-based compact model for nanoscale transistors. Physics-driven requirements on the neural network are discussed. Using finite element simulation as the input dataset, together with a neural network with roughly 30 neurons, the final IV model can well-predict the IV to within 1%. This modelling methodologies can be extended for other transistor properties such as capacitance-voltage (CV) characteristics, and the trained model can readily be implemented by the hardware description language (HDL) such as Verilog-A for circuit simulation. The EKV model [1-2] is used as an example. Other transistor models such as BSIM-MG [3] or PSP [4] model can also be used.

Fig: Architecture for the 3-layer neural network together with the aforementioned transformation T. Hyperbolic tangent function tanh(x) is used as the activation function for the input and hidden layers due to its infinite differentiability.

References:

[1] Enz, Christian C., Eric A. Vittoz; "Charge-based MOS transistor modeling." John Wiely & Sons Inc 68 (2006).

[2] FOSS EKV 2.6 Compact Model <https://github.com/ekv26/model>

[3] Khandelwal, Sourabh, et al. "BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control." IEEE Transactions on Electron Devices 59.8 (2012): 2019-2026.

[4] Gildenblat, G., et al. "PSP Model." Department of Electrical Engineering, The Pennsylvania State University and Philips Research, (Aug. 2005)

[Photos] MOS-AK LADEC Mexico April 18, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LAEDC Workshop

(virtual/online) April 18, 2021

Together with local Host and LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, we have organized the 3rd subsequent MOS-AK/LAEDC workshop which was the Virtual/Online event. There are a couple of the event photos:

MOS-AK Session 1 (APR.18) begun: 8:00am Mexico time zone (GMT-5)

T_1 FOSSEE eSIM: An open source CAD software for circuit simulation

Kannan Moudgalya

IIT Bombay (IN)

T_2 Memristor modeling

Arturo Sarmiento

INAOE (MX)

T_3 Modeling Issues for CMOS RF ICs

Roberto Murphy, Jose Valdes and Reydezel Torres

INAOE (MX)

T_4 Improving Time-Dependent Gate Breakdown of GaN HEMTs with p-type Gate

E. Sangiorgi, A. Tallarico, N. Posthuma, S. Decoutere, C. Fiegna

Universita di Bologna

MOS-AK Session 2 (APR.18) begun: 1:00pm Mexico time zone (GMT-5)

T_5 Compact Models of SiC and GaN Power Devices

Alan Mantooth, Arman Ur Rashid, Md Maksudul Hossain

University of Arkansas (US)

T_6 New analytical model for AOSTFTs

Antonio Cerdeira

CINVESTAV-IPN, Mexico City (MX)

T_7 On the Parameter Extraction of Thin-Film Transistors in Weak-Conduction

Adelmo Ortiz-Conde

Solid State Electronics Laboratory, Simon Bolivar University, Caracas (VE)

End of MOS-AK Workshop
Group Photo