Apr 13, 2021

[mos-ak] [Final Program] 3rd MOS-AK LAEDC Workshop (virtual/online) April 18, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
MOS-AK LAEDC Workshop
(virtual/online) April 18, 2021

Together with local Host and LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to the 3rd subsequent MOS-AK/LAEDC workshop which will be Virtual/Online event. Scheduled, MOS-AK/LAEDC workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK workshop program is available online: 
https://www.mos-ak.org/mexico_2021/

Venue: Virtual/Online MOS-AK Workshop - APRIL 18, 2021
  • Session 1 (APR.18) begins: 8:00am Mexico time zone (GMT-5)
  • Session 2 (APR.18) begins: 1:00pm Mexico time zone (GMT-5)
Online Free Registration is open, now:
https://forms.gle/PQgZk9td3Jeb4MWZ9
Registered participants will receive online meeting invitation 24h before the event. Any related enquiries can be sent to <wladek@mos-ak.org>

Postworkshop Publications: Selected best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics (SSE) issue on compact modeling.

W.Grabinski on the behalf of International MOS-AK Committee
WG13042021

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj8OWMvfqudPuDxVTCpSmy67415oD0%2BnxVdZaxZzdv5gwA%40mail.gmail.com.

[paper] Performance limits of hBN as an insulator for scaled CMOS

Theresia Knobloch1, Yury Yu. Illarionov1,2, Fabian Ducry3, Christian Schleich4, Stefan Wachter5, Kenji Watanabe6, Takashi Taniguchi7, Thomas Mueller5, Michael Waltl4, Mario Lanza8, Mikhail I. Vexler2, Mathieu Luisier3 and Tibor Grasser1
The performance limits of hexagonal boron nitride as an insulator for scaled CMOS devices based on two-dimensional materials
Nature Electronics; Vol 4; Feb.2021; pp.98–108;
DOI: 10.1038/s41928-020-00529-x

1. Institute for Microelectronics, TU Wien, Vienna, Austria.
2. Ioffe Institute, St Petersburg, Russia.
3. Integrated Systems Laboratory, ETH Zürich, Zurich, Switzerland.
4. Christian Doppler Laboratory for Single-Defect Spectroscopy in Semiconductor Devices at the Institute for Microelectronics, TU Wien, Vienna, Austria.
5. Institute for Photonics, TU Wien, Vienna, Austria.
6. Research Center for Functional Materials, National Institute for Matierals Science, Tsukuba, Japan.
7. International Center for Materials Nanoarchitectonics, National Institute for Materials Science, Tsukuba, Japan.
8. Physical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia.


Abstract: Complementary metal–oxide–semiconductor (CMOS) logic circuits at their ultimate scaling limits place extreme demands on the properties of all materials involved. The requirements for semiconductors are well explored and could possibly be satisfied by a number of layered two-dimensional (2D) materials, such as transition metal dichalcogenides or black phosphorus. The requirements for gate insulators are arguably even more challenging. At present, hexagonal boron nitride (hBN) is the most common 2D insulator and is widely considered to be the most promising gate insulator in 2D material-based transistors. Here we assess the material parameters and performance limits of hBN. We compare experimental and theoretical tunnel currents through ultrathin layers (equivalent oxide thickness of less than 1 nm) of hBN and other 2D gate insulators, including the ideal case of defect-free hBN. Though its properties make hBN a candidate for many applications in 2D nanoelectronics, excessive leakage currents lead us to conclude that hBN is unlikely to be suitable for use as a gate insulator in ultrascaled CMOS devices.
Fig: Comparison of gate insulators for ultrascaled CMOS devices based on 2D materials. a.) Currents at constant EOT for 3D oxides and layered insulators. The leakage currents as calculated with the Tsu–Esaki model are given for 3D amorphous oxide and 2D layered insulators at a constant thickness of EOT=0.76nm. If no tunnel masses were known, the free-electron mass was used. The filled circles indicate the results of ab initio calculations and the dotted line connecting the circles is a guide to the eye. b.) Currents at constant EOT for native oxides and fluorides. The leakage currents are given for native oxides and ionic fluorides at a constant thickness of EOT=0.76nm.

Acknowledgements: T.K., Y.Y.I. and T.G. acknowledge the financial support through FWF grant numbers I2606-N30, I4123-N30 and P29119-N35. Y.Y.I. and M.I.V. acknowledge financial support by the Ministry of Science and Higher Education of the Russian Federation under project number 075-15-2020-790. F.D. and M. Luisier thank CSCS for giving them access to the Piz Daint supercomputer under project number s876. C.S. and M.W. gratefully acknowledge financial support by the Austrian Federal Ministry for Digital and Economic Affairs and the National Foundation for Research, Technology and Development and the Christian Doppler Research Association. The computational results presented have been achieved in part using the Vienna Scientific Cluster (VSC). S.W. and T.M. acknowledge financial support through the Graphene Flagship number 785219 and number 881603. K.W. and T.T. acknowledge support from the Elemental Strategy Initiative conducted by the MEXT, Japan, number JPMXP0112101001, JSPS KAKENHI grant number JP20H00354 and the CREST(JPMJCR15F3), JST. M. Lanza acknowledges support from the Ministry of Science and Technology of China (grant numbers 2018YFE0100800, 2019YFE0124200) and the National Natural Science Foundation of China (grant number 61874075).

[papers] Compact Modeling

[1] Zhang, Yuanke, Tengteng Lu, Wenjie Wang, Yujing Zhang, Jun Xu, Chao Luo, and Guoping Guo. "Characterization and Modeling of Native MOSFETs Down to 4.2 K." arXiv:2104.03094 (2021).

Abstract: The extremely low threshold voltage (VTH) of native MOSFETs (VTH≈0 V @ 300 K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this paper, we characterize native MOSFETs within the temperature range from 300 K to 4.2 K. The cryogenic VTH increases up to ∼0.25 V (W/L = 10 µm/10 µm) and the improved subthreshold swing (SS) ≈ 14.30 mV/dec @ 4.2 K. The off-state current (IOFF) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different subbands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large size native MOSFETs suitable for the range of 300 K to 4.2 K. The mobility-related parameters are extracted via a machine learning approach and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs modeling and the design of cryogenic CMOS circuits for quantum chips.
Fig: I-V curves of native MOSFETs with W/L= 10/10µm measured (symbol) and calculated (solid line) at various temperatures. (a) Acomparison of the calculation results between this model and the  EKV2.6 model at 77K and 4.2K. (b) Measurement and calculation results of  the output characteristic at 4.2 K.

[2] Qixu Xie  Guoyong Shi; An analytical gm/ID‐based harmonic distortion prediction method for multistage operational amplifiers; Int J Circ Theor Appl. 2021; 1– 27. DOI: 10.1002/cta.3012

Abstract: An analytical stage‐based harmonic distortion (HD) analysis method for multistage operational amplifiers (Op Amps) is developed in this work. This work contributes two fundamental methods that make the analytical HD prediction possible at the circuit level. Firstly, we propose that the traditionally used first order small‐signal transistor quantities gm (transconductance) and go (output conductance) in the gm/ID design methodology for bulk complementary metal‐oxide‐semiconductor (CMOS) technology can be extended to the higher order quantities gm(k) and go(k) (k=1,2,3). With proper normalization, these quantities become neutral to the device dimensions and operation currents, hence can be precharacterized by sweeping simulations and used as lookup tables. Secondly, we further develop analytical nonlinearity expressions for a set of commonly used amplifier stages, represented as the functions of the nonlinearity parameters gm(k) and go(k) of the transistors that form a stage circuit. A combination of these two fundamental methods on hierarchical nonlinearity modeling enables us to apply the existing analytical HD estimation methods for the stage‐form macromodels to predict the circuit‐level HD behavior, overcoming the need of running repeated simulations under device resizing and rebiasing. The proposed harmonic distortion analysis method has been validated by application to real multistage amplifiers, achieving HD prediction results in excellent agreement to fully transistor‐level circuit simulation results but with substantial speedup.

Apr 12, 2021

White House to zero in on #chip shortage in meeting with company officials



from Twitter https://twitter.com/wladek60

April 12, 2021 at 05:22PM
via IFTTT