[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.

[paper] Compact Model of All-Optical-Switching Magnetic Elements

J. Pelloux-Prayer¹ and F. Moradi¹

Compact Model of All-Optical-Switching Magnetic Elements

IEEE TED, vol. 67, no. 7, pp. 2960-2965, July 2020

DOI: 10.1109/TED.2020.2991330.

¹Department of Engineering, Aarhus University, 8200 Aarhus, Denmark

Abstract: We present, for the first time, a Verilog-A compact model for an all-optically switchable magnetic tunnel junction (MTJ) using results of all-optical-switching (AOS) simulations. Our model is compatible with electronics and photonics design automation tools, and was tested using Cadence Specter and Virtuoso. This compact model can be used to design circuits and systems combining MTJs, photonic circuits, and electronic circuits giving the possibility to researchers working within this field to develop novel circuits and systems.

Fig: Equivalent circuit of the AOS model with LLGS module and LUT module.

Aknowledgement: This work was supported by the European Union’s Horizon 2020 Research and Innovation Programme under Grant 713481.

[paper] LF Noise Characterization of Ge n-Channel FinFETs

Alberto V. de Oliveira (Member, IEEE), Duan Xie (Member, IEEE), Hiroaki Arimura, Guillaume Boccardi, Nadine Collaert, Cor Claeys (Fellow, IEEE), Naoto Horiguchi (Member, IEEE)

and Eddy Simoen (Senior Member, IEEE_

Low-Frequency Noise Characterization of Germanium n-Channel FinFETs

IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2872-2877, July 2020

DOI: 10.1109/TED.2020.2990714

Abstract: This article presents an experimental, room temperature, low-frequency noise characterization of germanium n-channel fin-field-effect transistors (finFETs) integrated on silicon. After determining the dominant mechanism in the noise spectrum, the main parameters associated with the noise mechanism are extracted and evaluated as a function of fin width from a planar-like (100 nm) up to narrow fin (20 nm) for 1-µm length devices. The main findings are that the 1/f noise plays an important role in the Ge n-finFETs, whereby the trap density profiles in the gate-stack are quite uniform and have a lower level than in n-/p-channel Ge planar MOSFETs. In addition, a generation-recombination (GR) component was found in 160-nm-length devices, which is caused by GR centers located in the depletion region.

Fig: (a) Schematic of the Ge  n-finFET structure 

and (b) gate-stack composition

Fig: Drain current noise power spectral density as a function of frequency 

for a 160nm long Ge n-finFET

Acknowledgment: The authors would like to thank the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) and the Logic IIAP program for the support. This work has been performed in the frame of the imec Core Partner program on Ge devices.

[paper] Thyristor Conduction-Insulated Gate Bipolar Transistor

Mengxuan Jiang¹ (Member, IEEE) and Longjiang Gao¹

Simulation Study of a Thyristor Conduction-Insulated Gate Bipolar Transistor (TC-IGBT) 

with a p-n-p Base and an n-p-n Collector for Reducing Turn-Off Loss," 

IEEE TED, vol. 67, no. 7, pp. 2854-2858, July 2020

DOI: 10.1109/TED.2020.2995343

¹School of Electrical Engineering, Chongqing University, Chongqing 400044, China

Abstract: This article proposes a thyristor conduction-insulated gate bipolar transistor (TC-IGBT) with a p-n-p base and an n-p-n collector to reduce turn-off loss. The parasitic p-collector/n-drift/floating p (FP)-layer/carrier stored (CS)-layer thyristor is activated by the double channel gate and the p-n-p base acts a hole barrier to increase hole concentration at the top side. The n-p-n collector is used for extracting electrons from the n-drift region to decrease hole concentration at the bottom side. Therefore, these two effects form linear and descending hole concentration distribution profile. As a result, the p-n-p base and the n-p-n collector in the TC-IGBT offers lower turn-off loss and turn-off fall time. TCAD numerical simulations show reductions up to 47% (3.15 mJ) and 52% (34 ns) in turn-off loss and turn-off fall time, respectively, when compared to a field stop (FS) IGBT with similar breakdown voltage, threshold voltage, and short circuit time. Therefore, this designed structure may be attractive for power electronics applications.

Fig: (a) Proposed TC-IGBT and (b) its equivalent circuit model

Acknowledgment: This work was supported in part by the National Natural Science Foundation of China under Grant 51707025 and in part by the Chinese Universities Scientific Fund under Grant 106112017 CDJXY150099.

[paper] Unified Analytical Model for SOI LDMOS

Baoxing Duan, Jingyu Xing, Ziming Dong and Yintang Yang¹ (Senior Member, IEEE)

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

IEEE J-EDS, vol. 8, pp. 686-694, 2020

DOI: 10.1109/JEDS.2020.3006293

¹Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an 710071, China

Abstract: The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates the surface electric field by the electric field modulation effect to optimize the surface electric field distribution of the device. Also, the simulation results obtained through the simulation software ISE are consistent with the expected results of the analytical model. This not only proves the feasibility of the electric field modulation theory, but also shows that the accurate analytical model will be of great guiding significance for designing and optimizing the same LDMOS based on SOI structures.

FIG: Cross-sectional view of electric field modulated SOI LDMOS

Acknowledgment: This work was supported in part by Science Foundation for Distinguished Young Scholars of Shaanxi Province under Grant 2018JC-017, and in part by the 111 Project under Grant B12026.