[paper] Power Side-Channel Attacks in NCFET

Knechtel, Johann, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf,

Yogesh S. Chauhan, Jörg Henkel, Ozgur Sinanoglu, and Hussam Amrouch

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)

IEEE Micro, DOI 10.1109/MM.2020.3005883

Preprint arXiv:2007.03987 (2020)

Abstract: Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

Fig: (a) NCFET structure,with ferroelectric layer integrated inside the transistor’s gate stack;

(b) Equivalent caps series, where the internal voltage exhibits a greater voltage (V_int  > V_G)

Acknowledgments: This work was supported in part by the Center for Cyber Security (CCS) at New York University Abu Dhabi (NYUAD). The work of Satwik Patnaik was supported by the Global Ph.D. Fellowship at NYU/NYUAD. Besides, parts of this work were carried out on the HPC facility at NYUAD.

A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv #paper https://t.co/ZNrvrJN0Zd

A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv#paper pic.twitter.com/ZNrvrJN0Zd

— Wladek Grabinski (@wladek60) July 15, 2020

from Twitter https://twitter.com/wladek60

July 15, 2020 at 02:21PM
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[paper] First Principles Based Compact Model for 2D-Channel MOSFETs

Das, Biswapriyo, and Santanu Mahapatra

First Principles Based Compact Model for 2D-Channel MOSFETs

researchgate.net online publication

Abstract: We propose a generalized compact model for any two-dimensional material channel-based metal-oxide-semiconductor field-effect transistors. Unlike existing ones, the proposed model is first principles based and thus has ability to predict the circuit performance only using the crystallographic information of the channel material. It is ‘core’ in nature and developed following the industry-standard drift-diffusion formalism based ‘top-down’ hierarchy employing the FermiDirac statistics. We also implement the model in professional circuit simulator and good convergence is observed in 15-stage ring oscillator simulation.

Fig: Synopsis of the modeling framework. First, certain material specific parameters are extracted employing density functional theory computations and Hamiltonian calibration, which thereafter are used to develop the compact device model of the 2D-channel MOSFET using drift-diffusion formalism. The drain current and terminal charges obtained henceforth are used to implement digital circuits in commercial circuit simulator using its Verilog-AMS interface. 

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[RG] research paper reached 500 citations

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Wladek Grabinski¹, Marcelo Pavanello², Michelly de Souza², Daniel Tomaszewski³, Jola Malesinska³, Grzegorz Głuszko³, Matthias Bucher⁴, Nikolaos Makris⁴, Aristeidis Nikolaou⁴, Ahmed Abo-Elhadid⁵, Marek Mierzwinski⁶, Laurent Lemaitre⁷, Mike Brinson⁸, Christophe Lallement⁹, Jean-Michel Sallese¹⁰, Sadayuki Yoshitomi¹¹, Paul Malisse¹², Henri Oguey¹³, Stefan Cserveny¹³, Christian Enz¹⁰, François Krummenacher¹⁰ and Eric Vittoz¹⁰ 

in 49th European Solid-State Device Research Conference 

(ESSDERC; pp. 190-193)

DOI: 10.1109/essderc.2019.8901822 

FOSS EKV2.6 Verilog-A at GitHub https://github.com/ekv26/model

¹ MOS-AK Association (EU), 
² Centro Universitario FEI, Sao Bernardo do Campo (BR), 
³ Institute of Electron Technology, Warsaw (PL), 
⁴ Technical University of Crete, Chania (GR), 
⁵ Mentor Graphics (USA), 
⁶ Keysight Technologies (USA), 
⁷ Lemaitre EDA Consulting, 
⁸ London Metropolitan University (UK), 
⁹ ICube, Strasbourg University (F), 
¹⁰ EPFL Lausanne, 
¹¹ Toshiba (J), 
¹² Europractice/IMEC (B), 
¹³ CSEM S.A., Neuchatel (CH)

[paper] Carbon Nanotube Detectors and Spectrometers for the Terahertz Range

Junsung Park¹, Xueqing Liu¹, Trond Ytterdal²

and Michael Shur^1,3 

Carbon Nanotube Detectors and Spectrometers for the Terahertz Range 

Crystals 2020, 10, 601

DOI:10.3390/cryst10070601

¹Department of Electrical, Computer, and Systems Engineering, RPI  Troy, NY 12180, USA
²Department of Electronic Systems, NUST, O.S. Bragstads plass 2a, 7034 Trondheim, N
⁴Electronics of the Future, Inc., Vienna, VA 22181, USA

Abstract: We present the compact unified charge control model (UCCM) for carbon nanotube field-effect  transistors  (CNTFETs)  to  enable the accurate  simulation  of  the  DC  characteristics  and plasmonic terahertz (THz) response  in the  CNTFETs. Accounting for  the ambipolar  nature of the carrier transport (n-type and p-type conductivity at positive and negative gate biases, respectively), we use n-type and p-type CNTFET non-linear equivalent circuits connected in parallel, representing the ambipolar  conduction in the  CNTFETs.  This allows us to present a realistic non-linear  model that is valid across the  entire voltage  range  and is therefore suitable  for  the  CNTFET design. The important  feature  of  the  model  is that  explicit equations for gate  bias,  current,  mobility,  and capacitance with smoothing parameters accurately describe the device operation near the transition from above- to below-threshold regimes, with scalability in device geometry. The DC performance in  the proposed  compact CNTFET  model  is  validated  by  the  comparison between  the  SPICE simulation and the experimental DC characteristics. The simulated THz response resulted from the validated CNTFET model is found to be in good agreement with the analytically calculated response and  also  reveals  the  bias  and  power  dependent  sub-THz  response  and  relatively  wide  dynamic range   for   detection   that   could   be   suitable   for   THz   detectors.   The   operation   of   CNTFET spectrometers  in the THz  frequency  range  is  further  demonstrated  using  the  present  model.  The simulation exhibits that the CNT-based spectrometers can cover a broad THz frequency band from 0.1 to 3.08 THz. The model that has been incorporated into the circuit simulators enables the accurate assessment  of  DC  performance  and  THz  operation.  Therefore,  it  can  be  used  for the design  and performance estimation of the CNTFETs and their integrated circuits operating in the THz regime.  

Fig: Schematic illustration of the simulation circuit for the CNTFET THz detection

with the open boundary condition at the drain.

Funding: This  work  at  RPI  was  supported  by  the  U.S.  Army  Research  Laboratory  under  the  Cooperative Research Agreement (Project Monitor Dr. Meredith Reed) and by the US ONR (Project Monitor Dr. Paul Maki).