[paper] 1T-1C Dynamic Random Access Memory

1T-1C Dynamic Random Access Memory: 

Status, Challenges, and Prospects 

Alessio Spessot and Hyungrock Oh 

(Invited Paper)

IEEE TED, 67(4), 1382–1393

DOI:10.1109/ted.2020.2963911 

Abstract: This article reviews the status, the challenges, and the perspective of 1T-1C dynamic random access memory (DRAM) chip. The basic principles of the DRAM are presented, introducing the key functional aspects and the structure of modern devices. We present the most relevant historical trends for different modules of the memory chip, such as access device and storage element, reviewing some of the technological challenges faced by industry to guarantee the device shrinking imposed by the economic law. The most recent solutions introduced by the industry in modern DRAM devices for the critical elements are presented. Finally, a survey of the most critical bottleneck for future development is presented, reviewing some of the potential trends and perspectives of DRAM development.

Fig: Review of the historical evolution trend for the cell access device. Various cell access device options are shown. The 4F2 is enabled by the vertical channel. Corresponding technology nodes are included. 

Acknowledgment: The authors would like to thank the imec Core Partners Program for the support. They would also like to thank N. Horiguchi, A. Furnemont, M. H. Na, E. Dentoni Litta, R. Ritzenthaler, and M. Popovici from imec, P. Fazan and C. Mouli from Micron, and C. Kim, Y. Son, and Y. Ji from SK Hynix for the interesting discussions.

[paper] Atomistic Level Simulation of GaNFET

R. K. Nanda¹, E. Mohapatra¹, T. P. Dash¹, P. Saxena², P. Srivastava², R. Trigutnayat²
and C. K. Maiti¹

Atomistic Level Process to Device Simulation of GaNFET Using TNL TCAD Tools

chapter in Lecture Notes in Electrical Engineering book series (LNEE, volume 665)

doi:10.1007/978-981-15-5262-5 

¹Department of Electronics and Communication Engineering, Siksha ‘O’ Anusandhan, Bhubaneswar, Odisha 751030, India

²Tech Next Lab (P) Limited, Niwaz Ganj, Lucknow 226003, India

Abstract: An atomistic level process to device simulation tools developed by Tech Next Lab (TNL) is reported. Modeling of the deposition of high-quality ultrathin AlGaN epitaxial films grown on GaN substrates by molecular beam epitaxy (MBE) has been performed. The surface morphology, crystalline quality, and interfacial property of as-grown AlGaN epitaxial films on GaN substrates are studied using simulation. The epitaxial layer characterization for extract of exact carrier mobility and use of epitaxially grown material for GaN-FET device application has been demonstrated. Results obtained on the basis of process to device simulation have been calibrated with reported results.

Fig: Device structure with 25 nm thick AlGaN/GaN layer grown on SiC (100) substrate and its output Id –Vd characteristics

Learn more: http://www.technextlab.com/index.html

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[paper] Compact Model for SIS Josephson Junctions

A Compact Model for Superconductor-Insulator-Superconductor (SIS) Josephson Junctions

Shamiul Alam, Mohammad Adnan Jahangir and Ahmedullah Aziz, Member, IEEE

Department of Electrical Engineering and Computer Science

University of Tennessee, Knoxville, TN, USA

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2020.3002448

Abstract: We present a Verilog-A based compact model for the superconductor-insulator-superconductor (SIS) Josephson junction. The model can generate both hysteretic and non-hysteretic current-voltage (I-V) response for the SIS junctions utilizing the Stewart-McCumber damping parameter. We calibrate our model with different SIS samples and demonstrate accurate matching between the simulated and experimental results. We implement temperature effect on the energy gap and the critical current of the superconductor to explore the dynamic trends in device characteristics. We calculate the junction inductance and stored energy as functions of junction current and temperature. We simulate the read/write operations of an SIS junction based cryogenic memory cell to illustrate the usability of our model.

Fig: (a) Device structure of an SIS Josephson junction
(b) the RCSJ model of a Josephson junction.

[paper] 3D Vertical JL GAA Si Nanowire Transistors

Chhandak Mukherjee¹, Guilhem Larrieu² and Cristell Maneuxsup¹

Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors

EuroSOI-ULIS 2020, Sep 2020, Caen (F)

¹IMS Laboratory, University of Bordeaux, France

²LAAS-CNRS, Université de Toulouse, France 

HAL: hal.archives-ouvertes.fr/hal-02869216

Abstract: This paper presents a physics based, computationally efficient compact modeling approach for 3D vertical gate-all-around junctionless nanowire transistor (JLNT) arrays designed for future high performance computational logic circuit. The model features an explicit continuous analytical form adapted for a 14 nm channel JLNT technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary logic circuit simulations have been performed for benchmarking performances of transistor logic circuits, such as inverters and ring oscillators, designed using the developed model.

Fig: The vertical JLNT: (a) SEM image of nanowire arrays, 

(b) single nanowire showing its (c) gate formation 

Acknowledgement: This work is supported by ANR under Grant ANR-18- CE24-0005-01