[paper] Statistical modelling of oTFT

Faris, T. M. and Winscom, C. J. 

Statistical modelling of organic thin film transistor behaviour

Organic Electronics (2020, 105846

DOI:10.1016/j.orgel.2020.105846 

Abstract: Three analyses of the expressions describing the electrical characteristics of organic thin film transistors (OTFT's) are presented. The first is the field-independent approach to mobility originally used for inorganic semiconductor materials, often referred to as the Square Law (SQL). The second is appropriate for both the Multiple Trapping and Release (MTR) and the Variable Range Hopping (VRH) descriptions of mobility, where dependence on a transverse field is consistent with the Universal Mobility Law (UML). The third is appropriate for the Extended Gaussian Disorder (EGD) description where an exponential dependence of mobility on the transverse field occurs. In each case master equations have been derived, including Schottky contact effects, where the polarity of the voltage drop across the source and drain contacts is correctly taken into account for the first time. The effect of the bulk semiconductor material beyond the accumulation layer is also accounted for, and defines the sub-threshold performance in a low-voltage regime. A new statistical modelling procedure has been developed to extract the key parameters of these expressions simultaneously from experimental data. For the analysis of TRANSFER data, no more than five parameters are used in the SQL, UML and EGD treatments. All three models are considered so that the effect the choice of model has on the extracted parameters can be revealed; analysis of data from different metallophthalocyanines is used to illustrate the different effects. When the contact resistances correctly take into account possible Schottky-like behaviour, all three descriptions provide equally excellent fits to the data from TRANSFER experiments.  In a following report, a family of copper phthalocyanine-related semi-conductors will be examined in detail using these new analysis procedures to explore the effect of non-peripheral substituent bulk, and aza-nitrogen replacement by CH, on mobility.

Fig: Comparison of Ohmic-only vs. Ohmic+Schottky contact resistance extractions for

the linear region of GdPc2 TRANSFER data for VD=-5V

Acknowledgements: A. K. Ray (Brunel University, Uxbridge) and A. K. Sharma (USAF Research Laboratory) are gratefully acknowledged for providing some resources and experimental data. DZP Technologies Ltd., UK and USAF Research Laboratory, Space Vehicles Directorate, USA are thanked for sponsoring the project, and providing support to TMF.

[paper] Hot Carrier Degradation in n-MOSFETs

S. Mahapatra and U. Sharma, 

Department of Electrical Engineering,

IIT Bombay, Mumbai 400076, India

A Review of Hot Carrier Degradation in n-Channel MOSFETs

Part I: Physical Mechanism

IEEE TED, vol. 67, no. 7, pp. 2660-2671, July 2020

DOI: 10.1109/TED.2020.2994302

Abstract: Transistor parametric drift due to conduction mode hot carrier degradation (HCD) in n-MOSFETs is reviewed, for long- and short-channel length (LCH) devices having different source/drain (S/D) junction structures. The HCD magnitude and time kinetics shape are discussed for stress under different gate (VG) and drain (VD) biases with varying VG/VD ratio, and without and with substrate bias (VB). Post-dc stress kinetics is discussed. The published data are qualitatively analyzed to identify the roles of different underlying physical mechanisms. In part II of this article, impacts of technology scaling and stress temperature (T) and comparison of dc and ac stress are discussed.

Fig: (a) Schematic of an LDD MOSFET. Carrier heating process, primary and secondary impact ionization, respectively, at VB=0V and VB < 0V, and gate injection are shown. Charges due to HCD in the channel (square), gate–drain overlap (triangle), and spacer (diamond) regions are shown. (b) Energy band diagram showing the energy thresholds for impact ionization, and electron and hole injection over their respective channel-oxide barriers. AHI process is illustrated at (VG–VD) > 0V.

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[paper] AlGaN/AlN/GaN/AlGaN photodetector

Khaouani, M., Hamdoune, A., Bencherif, H., Kourdi, Z. and Dehimi, L. 

An ultra-sensitive AlGaN/AlN/GaN/AlGaN photodetector:

Proposal and investigation

Optik (2020). , 217, 164797

DOI:10.1016/j.ijleo.2020.164797 

Abstract: In this paper, an AlGaN/AlN/GaN/AlGaN photodetector high electron mobility transistor is designed and simulated. The proposed structure incorporates an AlN spacer layer between the AlGaN and GaN layers to ensure good control of the two-dimensional gas, which improve, in turn, the device controllability. Besides, an overall figures of merit assessment is performed to highlights the design benefits. The suggested device provides a very high responsivity of 0.2641 A/W, a photocurrent of 1.1 × 10−7 A, a suitable (Iilumination/Idark) rejection of 10.8, and a high efficiency η of about 77%. The photo and dark current is at 2 V, 87 mA and 8 mA, respectively. A subthreshold slope (SS) of 53 mV/V and 42 mV/V, and a transconductance gm of 260 ms/mm and 180 ms/mm are obtained. The proposed photodetector springly outperforms the HEMT PD designs previously proposed in the literature.

Fig: 2D-structure of AlGaN/AlN/GaN/AlGaN Photodetector HEMT

Acknowledgements: This work was supported by DGRSDT of Ministry of Higher education of Algeria. The work was done in the unit of research of materials and renewable energies (URMER).

[paper] Compact Modeling of Parasitic FET capacitance

Sharma, S. M., Singh, A., Dasgupta, S., & Kartikeyan, M. V. 

A review on the compact modeling of parasitic capacitance: 

from basic to advanced FETs. 

Journal of Computational Electronics

DOI: 10.1007/s10825-020-01515-4

Abstract: This paper presents a review on the development of parasitic-capacitance modeling for metal–oxide–semiconductor feldefect transistors (MOSFETs), covering models developed for the simple parallel-plate capacitance and the nonplanar and coplanar plate capacitances required for the intrinsic and extrinsic part of such devices. A comparative study of various extrinsic capacitance models with respect to a reference model is used to analyze the benefts of the various approaches. Capacitance models for basic MOSFETs and advance multigate FETs with two-dimensional (2D) and three-dimensional (3D) structures are reviewed. It is found that the elliptical feld lines between the gate electrodes and source/drain region are modeled very well, while deviations of ±2% in the orthogonal plate capacitance are observed when the gate electrode thickness is varied from 5 to 20nm.

Fig: The 3D structure of a FinFET

Acknowledgements: The authors would like to thank the Department of Electronics and Communication Engineering, IIT Roorkee, for their valuable support in carrying out this research work.