#OpenRAMAN: #OpenSource Raman Spectrometer Is Cheaper, But Not Cheap https://t.co/SAKV61rdou https://t.co/SotKelrOVK

#OpenRAMAN: #OpenSource Raman Spectrometer Is Cheaper, But Not Cheap https://t.co/SAKV61rdou pic.twitter.com/SotKelrOVK

— Wladek Grabinski (@wladek60) May 13, 2020

from Twitter https://twitter.com/wladek60

May 13, 2020 at 10:22AM
via IFTTT

[paper] Computing-in-Memory

Computing-in-Memory for Performance and Energy Efficient Homomorphic Encryption

Dayane Reis, Student Member, IEEE, Jonathan Takeshita, Taeho Jung, Member, IEEE, Michael Niemier, Senior Member, IEEE and Xiaobo Sharon Hu, Fellow, IEEE

preprint arXiv:2005.03002 (2020).

Abstract - Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory Processing (NMP) and Computing-in-memory (CiM) — paradigms where computation is done within the memory boundaries — represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications such as HE. This paper introduces CiM-HE, a Computing-in-memory (CiM) architecture that can support operations for the B/FV scheme, a somewhat homomorphic encryption scheme for general computation. CiM-HE hardware consists of customized peripherals such as sense amplifiers, adders, bit-shifters, and sequencing circuits. The peripherals are based on CMOS technology, and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against (i) two optimized CPU HE implementations, and (ii) an FPGA-based HE accelerator implementation.When compared to a CPU solution, CiM-HE obtains speedups between 4.6x and 9.1x, and energy savings between 266.4x and 532.8x for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-toend tasks, i.e., mean, variance, linear regression, and inference are up to 1.1x, 7.7x, 7.1x, and 7.5x faster (and 301.1x, 404.6x, 532.3x, and 532.8x more energy efficient). Compared to CPUbased HE in a previous work, CiM-HE obtain 14.3x speed-up and >2600x energy savings. Finally,our design offers 2.2x speed-up with 88.1x energy savings compared to a state-of-the-art FPGAbased accelerator.

Fig: Log shifter implemented in CiM-HE.

This work was supported in part by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Corresponding author: Xiaobo Sharon Hu, Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN, 46556, USA. e-mail: .

Conference Paper Reached 500 Reads

Wladek 

Wladek Grabinski, Daniel Tomaszewski, Farzan Jazaeri, Anurag Mangla, Jean-Michel Sallese, Maria-Anna Chalkiadaki, Antonios Bazigos, and Matthias Bucher

FOSS EKV 2.6 Parameter Extractor

22nd International MIXDES Conference, pp. 181-186 (2015)

Abstract: The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The EKV was developed especially to meet altogether the analog/RF design requirements. This paper describes a basic set of the DC parameter extraction steps for the EKV 2.6 model. The free open source software (FOSS) Profile2D tool was used to illustrate an accurate EKV 2.6 DC extraction strategy. 

[paper] BSIM-HV: High-Voltage MOSFET Model

H. Agarwal , Member, IEEE, C. Gupta , Graduate Student Member, IEEE, R. Goel , Graduate Student Member, IEEE, P. Kushwaha , Member, IEEE, Y.-K. Lin , Graduate Student Member, IEEE, M.-Y. Kao , Graduate Student Member, IEEE, J.-P. Duarte , Graduate Student Member, IEEE, H.-L. Chang , Member, IEEE, Y. S. Chauhan , Senior Member, IEEE, S. Salahuddin, Fellow, IEEE, and C. Hu, Life Fellow, IEEE

BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect

IEEE TED, vol. 66, no. 10, pp. 4258-4263, Oct. 2019

doi: 10.1109/TED.2019.2933611

Abstract - A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90V LDMOS and 40V VDMOS transistors, and shows excellent agreement.

FIG: Schematic of the LDMOS. Lightly doped n-region constitutes the drain. Majority of the applied drain voltage drops across this region, which protects the intrinsic transistor region from breakdown.

Manuscript received March 3, 2019; revised May 23, 2019 and July 24, 2019; accepted July 31, 2019. Date of publication August 26, 2019; date of current version September 20, 2019. This work was supported in part by the members of the Berkeley Center for Negative Capacitance Technology and the members of the Berkeley Device Modeling Center. The review of this article was arranged by Editor B. Iñiguez.

[paper] Compact Device Models for FinFET and Beyond

D. D. Lu, M. V. Dunga, A. M. Niknejad, C.Bing Hu, F.-X. Liang, W.-C. Hung, J. Lee, C.-H. Hsu
and M.-H. Chiang,

Compact device models for FinFET and beyond

ArXiv, vol. abs/2005.02580, 2020

Abstract - Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.

Fig: Simulation of a novel floating - gate synaptic transistor. (a) Device structure with separate negative feedback gate (nfb) for programming and synaptic gate (sg) readout. (b) Equivalent circuit diagram for compact modeling 

Acknowledgements - The authors would like to express sincere gratitude to Chip Implementation Center (CIC), Hsinchu, Taiwan for providing SPICE simulation environment for RRAM simulations.