#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
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Nov 2, 2017
#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
— Wladek Grabinski (@wladek60) November 2, 2017
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Oct 31, 2017
[mos-ak] [2nd Announcement and Call for Papers] 10th International MOS-AK Workshop in the Silicon Valley
10th International MOS-AK Workshop
(co-located with the CMC Meeting and IEDM Conference)
http://www.mos-ak.org/silicon_valley_2017/
Silicon Valley, December 6, 2017
2nd Announcement and Call for Papers
Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.
Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
Topics to be covered include the following among other related to the compact/SPICE modeling :
Online Workshop Registration
Postworkshop Publications:
Extended MOS-AK Committee
Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Important Dates:
- Call for Papers - Sept. 2017
- 2nd Announcement - Oct. 2017
- Final Workshop Program - Nov. 2017
- MOS-AK Workshop - Dec.6, 2017
Cadence Design Systems2655 Seely AveSan Jose, CA 95134
Topics to be covered include the following among other related to the compact/SPICE modeling :
- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, TFT, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS devices and circuits
- Technology R&D, DFY, DFT and reliability/ageing IC Designs
- Foundry/Fabless Interface Strategies
(any related inquiries can be sent to papers@mos-ak.org)
Online Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems
in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
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[paper] Review of physics-based compact models for emerging nonvolatile memories
Nuo Xu1, Pai-Yu Chen2, Jing Wang1, Woosung Choi1, Keun-Ho Lee3, Eun Seung Jung3, Shimeng Yu2
Review of physics-based compact models for emerging nonvolatile memories
1Device Lab, Samsung Semiconductor Inc., San Jose, CA 95134, USA
2School of ECEE, Arizona State University, Tempe, AZ 85281, USA
3Semiconductor R&D Center, Samsung Electronics, Hwasung-si, Gyeonggi-do, Korea
Journal of Computational Electronics, 2017, pp. 1-13
https://doi.org/10.1007/s10825-017-1098-0
Abstract: A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most promising emerging memory candidates: PCM, STT-MRAM, and RRAM to study their device physics as well as to evaluate their circuit-level performance. The models’ good predictability to experiments and their effectiveness in large-scale circuit simulation suggest their unique role in emerging memory research and development [read more...]
https://doi.org/10.1007/s10825-017-1098-0
SSCS Members Who Are 2017 IEEE Fellows
SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson
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