[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]

Multiple Honors for E3S Theme Leader, Professor Tsu-Jae King Liu

(March 1, 2017) –   The Center for Energy Efficient Electronics Science is proud to announce Prof. Tsu-Jae King Liu has been named a newly elected member of the National Academy of Engineering. Prof. King Liu, who leads the E³S Nanomechanics theme was elected this year as one of only three members from UC Berkeley to this highest professional honor to an engineer. Last year in August, Prof. King Liu has also been chosen to serve on the Board of Directors at Intel Corporation. She was welcomed by Intel Chairman Andy Bryant: “[Prof. King Liu] brings a wealth of expertise in silicon technology and innovation that will be valuable for Intel in many areas as we navigate a significant business transition while continuing to lead in advancing Moore’s Law and harnessing its economic value.”In addition to this distinguished honor by Intel, last year the Semiconductor Research Corporation (SRC) announced Prof. King Liu has been selected to receive the 2016 SRC Aristotle Award. This esteemed award was created by the SRC Board of Directors in March 1995 with the intent "to acknowledge outstanding teaching in its broadest sense, emphasizing student advising and teaching." Heartiest congratulations from the entire E³S community to Prof. King Liu for these prestigious honors!

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs

Abhijeet Walkea^a, Garrett Schlenvogtb^b, Santosh Kurineca^a

^aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA

^bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I_OFF <50pA/μm) and ultralow power (ULP) (I_OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I_OFF), transconductance (g_m), gate capacitance (C_gg) and intrinsic frequency (f_T). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

Rising SOI tide lifts Soitec into profit

Soitec SA (Bernin, France), developer of the "smart cut" method of silicon-on-insulator (SOI) wafer production, has reported its first profit for many years and is preparing to invest in facilities in France and possibly Singapore to meet rising demand for SOI wafers...

https://shar.es/1BtAZy


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[C4P] IEDM 2017

2017 IEDM CALL FOR PAPERS

The Annual International Electron Devices Meeting will be held at the Hilton San Francisco Union Square San Francisco, CA December 2-6, 2017

Abstract Deadline (four page final paper): August 2nd, 2017

To provide faster dissemination of the conference’s cutting-edge results, the abstract submission deadline has been moved to August 2nd for submission of four-page, camera-ready abstracts. Accepted papers will be published as-is in the proceedings

A Call for Papers flyer is available here: IEDM 2017 Call For Papers.

Customized Call for Papers for each of the technical subcommittee areas are also available:

• Circuit and Device Interaction (CDI)
• Characterization, Reliability, and Yield (CRY)
• Compound Semiconductor and High Speed Devices (CHS)
• Memory Technology (MT)
• Modeling and Simulation (MS)
• Material and interface modeling 
• Compact models
• Kinetic Monte Carlo and Molecular Dynamics
• Reliability and variability modeling
• Technology benchmarking
  New or trending areas include:
• First principle based quantum transport
• Process simulation with atomistic methods
• Self heating, interconnect and packaging
• Nano Device Technology (NDT)
• Optoelectronics, Displays, and Imagers (ODI)
• Power Devices (PD)
• Process and Manufacturing Technology (PMT)
• Sensors, MEMS, and BioMEMS (SMB)