Papers in Solid-State Electronics Volume 62, Issue 1, (August 2011)

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates   Original Research Article

Pages 31-39
Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu

Research highlights

► A computationally efficient approximation for surface potential in FDSOI MOSFETs is developed. ► I–V and C–V models for FDSOI MOSFETs are derived without making the charge sheet approximation. ► The core model and non-ideal effect expressions are implemented in Verilog-A language. ► The model is symmetric with respect to V_ds = 0 and continuous in all regions of operation.


 An effective thermal circuit model for electro-thermal simulation of SOI analog circuits   Original Research Article

Pages 48-61
Ming-C. Cheng, Kun Zhang

Highlights

► A thermal circuit model is developed for SOI analog circuits. ► The model integrates a device thermal circuit with interconnect thermal networks. ► The device thermal circuit accounts for non-isothermal effects in SOI devices. ► Thermal networks for cross-coupled and parallel coupled wires are developed. ► The model is coupled with BSIMSOI for electro-thermal simulation of SOI circuits.



MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 μm CMOS process   Original Research Article

Pages 115-122
P. Martin, A.S. Royet, F. Guellec, G. Ghibaudo

Research highlights

► Specific physical effects are observed in a cooled (77–200 K) 0.18 μm CMOS process. ► These effects are described and modeled for design of cryogenic IR CMOS imagers. ► Data on low frequency noise and transistor matching in MOSFET are also presented.



 Physics-based compact model for ultra-scaled FinFETs   Original Research Article

Pages 165-173
Ashkhen Yesayan, Fabien Prégaldiny, Nicolas Chevillon, Christophe Lallement, Jean-Michel Sallese

Highlights

► We propose a physical and explicit compact model for lightly doped FinFETs. ► This design-oriented model is valid for a large range of silicon Fin widths/lengths. ► It describes well the drain current, small signal parameters and capacitances. ► It takes into account all short-channel effects and quantum mechanical effects. ► This compact model needs a very few number of electrical parameters (4).



Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s   Original Research Article

Pages 174-184
Krishna Meel, R. Gopal, Deepak Bhatnagar

Highlights

► New 3-D front (back) gate threshold voltage models of FD-SOI MOSFETs are reported. ► Models solve 3-D Poisson’s equation using Green’s function as a tool. ► 3-D threshold voltage models include side wall, source/drain and back gate effects. ► Front and back gate charge coupling is incorporated in both the threshold voltages. ► Compact models of threshold voltages are amenable to circuit CAD tool.



Mobility analysis of surface roughness scattering in FinFET devices   Original Research Article

Pages 195-201
Jae Woo Lee, Doyoung Jang, Mireille Mouis, Gyu Tae Kim, Thomas Chiarella, Thomas Hoffmann, Gérard Ghibaudo

Highlights

► Mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. ► The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. ► The contribution of the surface roughness scattering was analysed and that on sidewalls was about three times stronger than on top surface for n-channel FinFETs.

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011

C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011
http://www.mos-ak.org/helsinki/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop in
Helsinki on Sept.16 2011 with special panel: 40th Anniversary of SPICE
(panelists tentative alphabetic list):
* Narain D. Arora, Siltera, USA
* Christian Enz, CSEM, CH
* Andrei Vladimirescu, EECS, Berkeley
* Andreas Wild, ENIAC - JU, EU
and MOS-AK/GSA Transistor Level IC Design Challenge Opening

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* VHDL-AMS/Verilog-A for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Transistor Level IC support
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by JUNE 30 http://www.mos-ak.org/helsinki/abstracts.php

Intending authors should also note the following deadlines:
* Announcement and Call for Papers - May 2011
* on-line abstract submission deadline - June 30, 2011
* Final Workshop Program - August 2011
* MOS-AK/GSA Workshop - Sept. 16, 2011

On-line workshop registration: http://www.essderc2011.org/registration.php
Further details and updates: http://www.mos-ak.org/helsinki
Email contact: helsinki@mos-ak.org

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Papers for curious people... (may 25th 2011)

CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability

Stanzione, S.  Puntin, D.  Iannaccone, G. 
Page(s): 1456 - 1463
Digital Object Identifier : 10.1109/JSSC.2011.2120650

AbstractPlus | Full Text: PDF (1209KB)

This paper presents an extreme-low-power mixed-signal CMOS integrated circuit for product identification and anti-counterfeiting, which implements a physical unclonable function operating with a challenge-response scheme. We devise a series of circuits and algorithmic solutions based on the use of a process monitor and on the prediction of the erratic response bits which allow to suppress the effects of temperature, voltage supply and process variations in order to obtain a robust and reliable b... Read More »


 

A Supply-Rail-Coupled eTextiles Transceiver for Body-Area Networks

Mercier, P. P.  Chandrakasan, A. P. 
Page(s): 1284 - 1295
Digital Object Identifier : 10.1109/JSSC.2011.2120690

AbstractPlus | Full Text: PDF (1915KB)

This paper presents a transceiver that communicates over electronic textiles as an alternative, energy-efficient communication medium for body-area network (BAN) applications. The proposed eTextiles network architecture consists of a two-wire conductive yarn medium, body-worn nodes, and a basestation used for data collection and medium-access control. Fabricated in 0.18 $mu$m CMOS technology, the eTextiles transceiver employs supp... Read More »

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

Ye, Y.  Liu, F.  Chen, M.  Nassif, S.  Cao, Y. 
Page(s): 987 - 996
Digital Object Identifier : 10.1109/TVLSI.2010.2043694

Abstract | Full Text: PDF (1332KB)

The threshold voltage $({V}_{rm th})$ of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant ... Read More »

On Functional Broadside Tests With Functional Propagation Conditions

Pomeranz, I.  Reddy, S. M. 
Page(s): 1094 - 1098
Digital Object Identifier : 10.1109/TVLSI.2010.2043695

AbstractPlus | Full Text: PDF (197KB)

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As a result, it avoids overtesting that may occur with unreachable states. However, the scan-out operation at the end of a functional broadside test allows the observation of any fault effects that reached the state variables at the end of the secon... Read More »

 

Broadside and Functional Broadside Tests for Partial-Scan Circuits

Pomeranz, I.  Reddy, S. M. 
Page(s): 1104 - 1108
Digital Object Identifier : 10.1109/TVLSI.2010.2044049

AbstractPlus | Full Text: PDF (176KB)

Functional broadside tests were defined to address overtesting that may occur due to the detection of delay faults under nonfunctional operation conditions. Such conditions are made possible by scanning in unreachable states. Functional broadside tests were defined and studied in the context of full-scan circuits. In this work, we study the definition of broadside and functional broadside tests in partial-scan circuits. A unique property we show is that if the unscanned state variables are obser... Read More »

Papers in IEEE TED, vol 58, issue 6 (june 2011)

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Jandhyala, S.  Mahapatra, S. 
Page(s): 1663 - 1671
Digital Object Identifier : 10.1109/TED.2011.2131654

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in ... Read More »

Statistical Model of Line-Edge and Line-Width Roughness for Device Variability Analysis

Hiraiwa, A.  Nishida, A.  Mogami, T. 
Page(s): 1672 - 1680
Digital Object Identifier : 10.1109/TED.2011.2131144

The authors propose a model of line-edge and line-width roughness (LER and LWR) of actual device patterns, which received some smoothing steps, for accurate estimation of device variability. The model assumes that LER/LWR has originally an exponential autocorrelation function (ACF) and is smoothed using another exponential function. The power spectrum of this ACF almost completely fits the experimental one of polycrystalline silicon lines, which were formed using plasma etching. The authors inve... Read More »

A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

Bazigos, A.  Krummenacher, F.  Sallese, J.-M.  Bucher, M.  Seebacher, E.  Posch, W.  Moln??r, K.  Tang, M. 
Page(s): 1710 - 1721
Digital Object Identifier : 10.1109/TED.2011.2119487

This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal–oxide–semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standar... Read More »

Papers in IEEE EDL, vol 32, issue 6 (may 2011)

Modeling of Current-Return-Path Effect on Single-Ended Inductor in Millimeter-Wave Regime

Wang, H.  Zhang, L.  Yang, D.  Zeng, D.  Wang, Y.  Yu, Z. 
Page(s): 737 - 739
Digital Object Identifier : 10.1109/LED.2011.2136312

The effect of current return path (CRP) on the accurate modeling of single-ended inductors in the millimeter-wave regime has been investigated. A series of spiral inductors with different sizes, shapes, and CRP positions was fabricated in a 0.18-$muhbox{m}$ RF-CMOS process and measured up to 50 GHz. An analytical appended model for CRP is developed to characterize the effect, and its equivalent circuit is validated by measurement ... Read More »

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Duarte, J. P.  Choi, S.-J.  Moon, D.-I.  Choi, Y.-K. 
Page(s): 704 - 706
Digital Object Identifier : 10.1109/LED.2011.2127441

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk curre... Read More »

Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source–Drain Resistances in MOSFETs

Bae, H.  Jang, J.  Shin, J. S.  Yun, D.  Lee, J.  Kim, T. W.  Kim, D. H.  Kim, D. M. 
Page(s): 722 - 724
Digital Object Identifier : 10.1109/LED.2011.2131116

A new technique for a separate extraction of the current-path-dependent resistance $(R_{{rm SD}0})$ from the contact-dependent source and drain resistances $(R_{rm Se} hbox{and} R_{rm De})$ is reported for a single MOSFET. We also report a technique for a separation of $V_{rm GS}$ -dependent source an... Read More »

Extraction of Separated Source and Drain Resistances in Amorphous Indium–Gallium–Zinc Oxide TFTs Through – Characterization

Bae, H.  Kim, S.  Bae, M.  Shin, J. S.  Kong, D.  Jung, H.  Jang, J.  Lee, J.  Kim, D. H.  Kim, D. M. 
Page(s): 761 - 763
Digital Object Identifier : 10.1109/LED.2011.2127438

Considering asymmetry caused by layout, process, and device degradation, separate extraction of the source and drain resistances, i.e., $R_{S}$ and $R_{D}$, respectively, from the total resistance $R_{rm TOT}$ is very important in the design, modeling, and characterization of amorphous indium–g... Read More »

Mechanism Analysis of Off-Leakage Current in an LDD Poly-Si TFT Using Activation Energy

Nakashima, A.  Kimura, M. 
Page(s): 764 - 766
Digital Object Identifier : 10.1109/LED.2011.2132112

We have analyzed the mechanism of off-leakage current in an lightly doped drain (LDD) poly-Si thin-film transistor by investigating the activation energy $E_{a}$. It is found that $E_{a}$ decreases as the gate and drain voltages increase. We have also discussed the mechanism using a device simulator. It is found that a hole channel is lightly formed in the LDD regio... Read More »

Evidence of a Novel Source of Random Telegraph Signal in CMOS Image Sensors

Goiffon, V.  Magnan, P.  Martin-Gonthier, P.  Virmontois, C.  Gaillardin, M. 
Page(s): 773 - 775
Digital Object Identifier : 10.1109/LED.2011.2125940

This letter reports a new source of dark current random telegraph signal in CMOS image sensors due to meta-stable Shockley–Read–Hall generation mechanism at oxide interfaces. The role of oxide defects is discriminated thanks to the use of ionizing radiations. A dedicated RTS detection technique and several test conditions (radiation dose, temperature, integration time, photodiode bias) reveal the particularities of this novel source of RTS. Read More »


 

Temperature Dependence of the Threshold Voltage Shift Induced by Carrier Injection in Integrated STI-Based LDMOS Transistors

Poli, S.  Reggiani, S.  Denison, M.  Gnani, E.  Gnudi, A.  Baccarani, G.  Pendharkar, S.  Wise, R. 
Page(s): 791 - 793
Digital Object Identifier : 10.1109/LED.2011.2135835

Large threshold voltage shifts $(Delta V_{t})$ are experimentally observed in n-channel lateral DMOS transistors under high current–voltage regime. The effect is enhanced by the gate voltage as well as by the ambient temperature $(T_{A})$ . By approximating the curves with the usually adopted power-law dependence ... Read More »

RF Model and Verification of Through-Silicon Vias in Fully Integrated SiGe Power Amplifier

Liao, H.-Y.  Chiou, H.-K. 
Page(s): 809 - 811
Digital Object Identifier : 10.1109/LED.2011.2136313

This letter proposes an RF model of through-silicon via (TSV) considering both skin-depth and lossy substrate effects up to 20 GHz. The TSV is fabricated in 0.18-$muhbox{m}$ SiGe BiCMOS process with the dimensions of 50 $muhbox{m}$ in diameter and 100 $muhbox{m}$ in depth. The equivalent circuit model... Read More »

Channel-Length-Dependent Transport Behaviors of Graphene Field-Effect Transistors

Han, S.-J.  Chen, Z.  Bol, A. A.  Sun, Y. 
Page(s): 812 - 814
Digital Object Identifier : 10.1109/LED.2011.2131113

This letter presents a detailed study of transport in graphene field-effect transistors (GFETs) with various channel lengths, from 5 $muhbox{m}$ down to 90 nm, using transferred graphene grown by chemical vapor deposition. An electron–hole asymmetry observed in short-channel devices suggests a strong impact from graphene/metal contacts. In addition, for the first time, we observe a shift of the gate voltage at the Dirac poi... Read More »