Thursday, June 2, 2011

Papers in Solid-State Electronics Volume 62, Issue 1, (August 2011)

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates   Original Research Article

Pages 31-39
Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu

Research highlights

► A computationally efficient approximation for surface potential in FDSOI MOSFETs is developed. ► IV and CV models for FDSOI MOSFETs are derived without making the charge sheet approximation. ► The core model and non-ideal effect expressions are implemented in Verilog-A language. ► The model is symmetric with respect to Vds = 0 and continuous in all regions of operation.

 An effective thermal circuit model for electro-thermal simulation of SOI analog circuits   Original Research Article

Pages 48-61
Ming-C. Cheng, Kun Zhang


► A thermal circuit model is developed for SOI analog circuits. ► The model integrates a device thermal circuit with interconnect thermal networks. ► The device thermal circuit accounts for non-isothermal effects in SOI devices. ► Thermal networks for cross-coupled and parallel coupled wires are developed. ► The model is coupled with BSIMSOI for electro-thermal simulation of SOI circuits.

MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 μm CMOS process   Original Research Article

Pages 115-122
P. Martin, A.S. Royet, F. Guellec, G. Ghibaudo

Research highlights

► Specific physical effects are observed in a cooled (77–200 K) 0.18 μm CMOS process. ► These effects are described and modeled for design of cryogenic IR CMOS imagers. ► Data on low frequency noise and transistor matching in MOSFET are also presented.

 Physics-based compact model for ultra-scaled FinFETs   Original Research Article

Pages 165-173
Ashkhen Yesayan, Fabien Prégaldiny, Nicolas Chevillon, Christophe Lallement, Jean-Michel Sallese


► We propose a physical and explicit compact model for lightly doped FinFETs. ► This design-oriented model is valid for a large range of silicon Fin widths/lengths. ► It describes well the drain current, small signal parameters and capacitances. ► It takes into account all short-channel effects and quantum mechanical effects. ► This compact model needs a very few number of electrical parameters (4).

Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s   Original Research Article

Pages 174-184
Krishna Meel, R. Gopal, Deepak Bhatnagar


► New 3-D front (back) gate threshold voltage models of FD-SOI MOSFETs are reported. ► Models solve 3-D Poisson’s equation using Green’s function as a tool. ► 3-D threshold voltage models include side wall, source/drain and back gate effects. ► Front and back gate charge coupling is incorporated in both the threshold voltages. ► Compact models of threshold voltages are amenable to circuit CAD tool.

Mobility analysis of surface roughness scattering in FinFET devices   Original Research Article

Pages 195-201
Jae Woo Lee, Doyoung Jang, Mireille Mouis, Gyu Tae Kim, Thomas Chiarella, Thomas Hoffmann, Gérard Ghibaudo


► Mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. ► The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. ► The contribution of the surface roughness scattering was analysed and that on sidewalls was about three times stronger than on top surface for n-channel FinFETs.

No comments: