[paper] Analog System Synthesis for Reconfigurable Computing

Afolabi Ige, Linhao Yang, Hang Yang, Jennifer Hasler, and Cong Hao

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

J. Low Power Electron. Appl. 2023, 13, 58. 

DOI: 10.3390/jlpea1304005

* Electrical and Computer Engineering (ECE), Georgia Institute of Technology (USA)

Abstract: The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.

Figure: The analog synthesis tool flow to generate a design on a large-scale Field Programmable Analog Array (FPAA) or an Application-Specific Integrated Circuit (ASIC). A single user-supplied high-level description goes through multiple lowering steps to reach the targeted output, either GDSII or a switch list. For targeting an FPAA, a design can either be specified through the GUI in XCOS (a pre-existing flow) or through the new text-based Python flow. Users construct circuits and systems using class objects provided in the Python cell library that mirror the palette browser in the XCOS library, and the description is then lowered into a Verilog syntax. The FPAA path lowers to Blif netlist, fitting into our preexisting flow compiling a switch list to target the FPAA. For targeting an ASIC, users perform similar steps to construct a system from Python objects with cells made available in the provided library. Those Python objects are then converted to a Verilog netlist before being fed to the layout synthesis modules, which handle placement and global routing. These serve as inputs to the open-source detailed router (TritonRoute) to convert the guide to a path. That path is merged with the placement file to create a final output layout file.

Funding: Partial funding for the development of this effort came from NSF (2212179).

[paper] DEVSIM

Sanchez, J. E.,

DEVSIM: A TCAD Semiconductor Device Simulator

Journal of Open Source Software, 7(70), 3898, (2022).

DOI:10.21105/joss.03898

Abstract: DEVSIM is technology computer-aided design (TCAD) software for semiconductor device simulation. By solving the equations for electric fields and current flow, it simulates the electrical behavior of semiconductor devices, such as transistors. It can be used to model existing, fabricated devices for calibration purposes. It is also possible to explore novel device structures and exotic materials, reducing the number of costly and time-consuming manufacturing iterations While DEVSIM has limited capabilities for the creation of 1-D and 2-D meshes, the Pythoninterface allows the import of mesh structures from any format using a triangular representation (in 2-D) or a tetrahedral representation (in 3-D). This makes it possible for the user to utilize high quality open source meshing solutions.

FIG: 90-nm 3-D MOSFET. The polysilicon gate (2) is surrounded by oxide (5) and two nitride regions (3) and (4). The bulk region (1) has a 120nm drawn gate length. The source and drain contacts are both 50 nm underneath the nitride regions. A body contact was placed on the bottom of the 60nm silicon region. The oxide thickness is 4.9 nm and the device is 25nm thick.

[paper] STT-MTJ Device Model

Haoyan Liu and Takashi Ohsawa
General-Purpose STT-MTJ Device Model Based on the Fokker-Planck Equation
IEEE Transactions On Nanotechnology, VOL. 22, 2023 659 A
DOI: 10.1109/TNANO.2023.3322468.

Graduate School of Information, Production and Systems, Waseda University (J)

Abstract: A thermally agitated device model of spin-transfer torque magnetic tunnel junction (STT-MTJ) based on the Fokker-Planck equation is proposed which is implemented into HSPICE by using Verilog-A. We compared different techniques of finite difference method (FDM) and analyzed the impact of the solvers on computational efficiency and accuracy. A framework is proposed which traces dynamics of a particular STT-MTJ’s angle between the magnetic moments of the free and the pinned layers and makes the model applicable to a wide range of circuits. The model was applied to the 4T2MTJ memory cell array and a leaky integrate and-fire (LIF) neuron circuit to validate the stochastic switching characteristic and the angle prediction function. In the memory array simulations, the CPU time consumption for this model is 1/30 of the model which is based on the stochastic Landau-Lifshitz Gilbert-Slonczewski equation.

Fig: (a) Structure of 1T1MTJ synapse. (b) Binary weights in 10 neurons and an input digit ‘9’ of spiking neural network (surrounded by the dotted square) used for the experiment shown. Each digit is a 28×28 matrix. Each figure shows two output spikes fired in the neurons representing ‘0-9’. The total spike numbers of the neurons which represent 0-9 are 2, 3, 4, 3, 4, 4, 4, 4, 4 and 9. 

Acknowledgement: This work was supported in part by Synopsys Corporation, in part by JSPS KAKENHI under Grant JP20K04626, in part by VLSI Design and Education Center (VDEC), University of Tokyo with collaboration with Cadence Corporation, and in part by the cooperation of organization between Kioxia Corporation and Waseda University.

[chapter] Extraction for a 65nm FG Transistor.

[chapter] Cong, T.D., Hoang, T. (2023). A Methodology of Extraction DC Model for a 65 nm Floating-Gate Transistor. 

In: Dao, NN., Thinh, T.N., Nguyen, N.T. (eds) Intelligence of Things: Technologies and Applications. ICIT 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 187. Springer, Cham. https://doi.org/10.1007/978-3-031-46573-4_19

Abstract: Floating-gate Metal-Oxide Semiconductor (MOS) has been investigated and applied in many applications such as artificial intelligence, analog mixed-signal, neural networks, and memory fields. This study aims to propose a methodology for extracting a DC model for a 65 nm floating-gate MOS transistor. The method in this work uses the combination architecture of MOS transistor, capacitance, and voltage-controlled voltage source which can archive a high accuracy result. Moreover, the advantage of the method is that the MOS transistor was a completed model which enhances the flexibility and accuracy between a fabricated device and modeled architecture. In our work, the industrial standard model Berkeley Short-channel IGFET Model (BSIM) 3v3.1, level 49 was deployed, and the DC simulation was obtained with the use of LTspice tool.

[book] Microelectronic Circuits

Sedra, Adel S., Smith, Kenneth Carless, Carusone, 

Tony Chan, Gaudet, Vincent. 

Microelectronic Circuits. 

United Kingdom: Oxford University Press, 2020

Circuits by Sedra and Smith has served generations of electrical and computer engineering students as the best and most widely-used text for this required course. Respected equally as a textbook and reference, "Sedra/Smith" combines a thorough presentation of fundamentals with an introduction to present-day IC technology. It remains the best text for helping students progress from circuit analysis to circuit design, developing design skills and insights that are essential to successful practice in the field. Significantly revised with the input of two new coauthors, slimmed down, and updated with the latest innovations, Microelectronic Circuits, Eighth Edition, remains the gold standard in providing the most comprehensive, flexible, accurate, and design-oriented treatment of electronic circuits available today.

Appendix

• B. SPICE Device Models and Design with Simulation Examples

Model files for representative CMOS technologies are provided below:

• 0.8 um CMOS
• 0.35 um CMOS
• 0.18 um CMOS
• 45 nm CMOS
• 7nm FinFET