Niharika Thakuria, Graduate Student Member, IEEE, Daniel Schulman, Member, IEEE, Saptarshi Das, Member, IEEE, and Sumeet Kumar Gupta, Member, IEEE
2D Strain FET (2D-SFET) Based SRAMs - Part I: Device-Circuit Interactions
IEEE TED, vol. 67, no. 11, pp. 4866-4874, Nov. 2020
DOI: 10.1109/TED.2020.3022344.
Abstrat: In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to 2.7× larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing VB-enabled SRAM designs.
Fig: 2D-SFET model with bandgap reduction and 2-D-electrostatics [18]. COX, CGS/D,F, CIT, and CGB are oxide, gate (G) to source (S)/drain (D) fringe, trap, and PE capacitance, respectively. VFB, and VFBS are flat-band voltage of G and back contact. VQFL(VS,VD) is S/D quasiFermi level. ΔEG(VG'B) is VGB dependent bandgap change, τEG is strain transduction delay, and REG is resistance used to model τEG. ΔEG(τEG) is final bandgap reduction considering τEG, used for calculating channel charge, QCH(ΔEG(τEG)).
Aknowlegement: This work was supported in part by NSF under Grant 1640020, in part by Nanoelectronics Research Corporation (NERC), and in part by Semiconductor Research Corporation (SRC) under Grant 2699.003
