[paper] IGBT Compact Modeling

Compact Modeling of IGBT Charging/Discharging for Accurate Switching Prediction

Y. Miyaoku¹, A. Tone¹, K. Matsuura¹, M. Miura-Mattausch¹ (Fellow, IEEE),

H. J. Mattausch¹ (Senior Member, IEEE), and D. Ikoma²

IEEE J-EDS, vol. 8, pp. 1373-1380, 2020

doi: 10.1109/JEDS.2020.3008919

1 Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi-Hiroshima 739-8527, Japan
2 Sensor and Semiconductor Development, Denso Corporation, Aichi 448-8661, Japan

ABSTRACT The trench-type IGBT is one of the major devices developed for very high-voltage applications, and has been widely used for the motor control of EVs as well as for power-supply systems. In the reported investigation, the accurate prediction of the power dissipation of IGBT circuits has been analyzed. The main focus is given on the carrier dynamics within the IGBTs during the switching-off phase. It is demonstrated that discharging and charging at the IGBT’s gate-bottom-overlap region, where electron discharging is followed by hole charging, has an important influence on the switching performance. In particular, the comparison of long-base and short-base IGBTs reveals, that a quicker formation of the neutral region within the resistive base region, as occurring in the long-base IGBT, leads to lower gatebottom-overlap capacitance, thus realizing faster electron discharging and hole charging of this overlap region.

FIG: IGBT structures with nMOSFET + pnp BJT part (a. and b.) and nMOSFET-only structure (c.). The X–Y line is through the middle of the bottom-gate oxide and the A–B line is directly underneath the bottom-gate oxide.

Received 14 May 2020; revised 2 July 2020; accepted 8 July 2020. Date of publication 13 July 2020; date of current version 8 December 2020. The review of this article was arranged by Editor M. Mierzwinski. Digital Object Identifier 10.1109/JEDS.2020.3008919

[paper] Compact Models for Sizing Based on ANN

Husni Habal, Dobroslav Tsonev, Matthias Schweikardt 

Compact Models for Initial MOSFET Sizing Based on Higher-order Artificial Neural Networks

ACM/IEEE Workshop on Machine Learning for CAD (MLCAD ’20)

Nov. 16–20, 2020, Virtual Event, Iceland. ACM, pp. 111-116

DOI: 10.1145/3380446.3430632

¹Infineon Technologies AG Munich, Germany
²LogiqWorks Ltd. Sofia, Bulgaria
³Reutlingen University Reutlingen, Germany

Abstract: Simple MOSFET models intended for hand analysis are inaccurate in deep sub-micrometer process technologies and in the moderate inversion region of device operation. Accurate models, such as BSIM6 model, are too complex for use in hand analysis and are intended for circuit simulators. Artificial neural networks (ANNs) are efficient at capturing both linear and non-linear multivariate relationships. In this work, a straightforward modeling technique is presented using ANNs to replace the BSIM model equations. Existing open-source libraries are used to quickly build models with error rates generally below 3%. When combined with a novel approach, such as the gm/Id systematic design method, the presented models are sufficiently accurate for use in the initial sizing of analog circuit components without simulation.

Figure: ANN Model Architecture.

[paper] Compact Model for Power MOSFET

Abdelghafour Galadi

PSPICE compact model for power MOSFET based on manufacturer datasheet

DOI:10.1088/1757-899X/948/1/012007

National School of Applied Sciences of Safi, Cadi Ayyad University, Marrakech (MA)

Abstract: In this paper, large signal model for power MOSFET devices is presented. The proposed model includes quasi-saturation effect and describes accurately the electrical behavior of the power MOSFET devices. The large signal model elements will be provided based on the device structure. Furthermore, the model parameters are extracted from measurements considering the voltages depending effect of the nonlinear gate-source, gate-drain and drain-source interelectrode capacitances. Excellent agreements will be shown between the simulated and the datasheet data. Finally, a description of the model will be provided along with the parameter extraction procedure.

Fig: a) Conventional power MOSFET structure with b) its subcircuit elements. 

[paper] Optomechanical Sensor in Verilog-A

Houssein Elmi Dawale, Loïc Sibeud, Sébastien Regord, Guillaume Jourdan, Member, IEEE, Sébastien Hentz, Member, IEEE, and Franck Badets, Senior Member, IEEE

Compact Modeling and Behavioral Simulation of an Optomechanical Sensor in Verilog-A

IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4677-4681, Nov. 2020

DOI: 10.1109/TED.2020.3024477

Abstract: Previous work has shown that optomechanical resonators are particularly well suited to the design of ultrasensitive mass sensors. They present an extremely low noise level, very high optical quality factor (Q>105), excellent integration density and can resonate both in a gaseous and liquid environment. In order to reduce the long measurement time due to their small particle capture area, several such resonators must be integrated onto the same chip. However, bulky laboratory equipment currently used to read a single optomechanical resonator cannot be practically scaled up to a large array of transducers. It is then required to design and eventually integrate a read-out interface that can process tens to thousands of resonators. To ease the design of such a circuit, this article presents a compact analytical model of an electrostatically actuated optomechanical resonator implemented in Verilog-A. The proposed model includes both the optical and mechanical behaviors, as well as optomechanical coupling and thermo-optical effect. It was simulated in commercial simulator and is consistent with the measured results. 

FIG: a) General view of the optomechanical device with electrostatic actuation. 

b) Functional diagram of the device in Verilog-A.

[paper] Parameter Extraction Technique for IGBT Compact Model

N.V. Bharadwaj¹, Dr. P. Chandrasekhar² and Dr. M. Sivakumar³

A Consecutive Parameter Extraction Technique for IGBT Compact Model

ICMM-2019; AIP Conf. Proc. 2269, 030031-1–030031-5;

DOI: 10.1063/5.0019484

¹Geethanjali College of Enegineering and Technology, Hyderabad, 501301, India 

²MGIT, Hyerabad, 500075, India 

³Gudlavalleru Engineering College, Gudlavalleru , 521356, India

Abstract: A consecutive parameter extraction technique describes the fitting target related parameters for Insulated-gate bipolar transistor (IGBT) model. The IGBT model has been represented by a couple of simplified equivalent circuits. Using simulated data for a trench-type IGBT as reference the performance of compact model IGBT is compared to an IGBT macro model. Due to physics based modeling, parameter extraction with the compact model is fast. With very less extraction effort, the compact model fits the dc current and capacitance characteristics accurately.

FIG: The IGBT cell structure with cell pitch = 4μm and trench gate depth = 3μm

[paper] TFT Compact Model of AMOLEDs Image‐Retention

A Novel Charge Based TFT Compact Model Applicable 

to Image‐Retention Simulation of AMOLEDs

Genshiro Kawachi 

Tianma Japan Ltd., Kanagawa, Japan

SID Symposium Digest of Technical Papers, 51(1), 1390–1393. 

P‐193: Late‐News‐Poster; First published: 25 September 2020

DOI: 10.1002/sdtp.14145

Abstract: A novel TFT compact model based on surface potential and charge calculations has been developed. Two kinds of non‐quasi‐static (NQS) models are included to describe the transient effects of TFTs. Appling the new model, accurate simulation of image retention phenomena in AMOLEDs was realized.

Fig: Transient response of a 2T1C pixel circuit (a) after switching from black to gray level: (b) simulation assuming a distributed τ_NQS model and measured results are compared.

[paper] Compact Models for IGBTs

Advanced physics-based compact models for new IGBT technologies

Arnab Biswas, Maria Cotorogea

Infineon Technologies AG, Germany

Abstract The TRENCHSTOP™ IGBT7 technology is based on the latest micro-pattern trench technology. It provides strongly reduced losses offering a high level of controllability [1]. This technology brings forward new challenges in compact modelling. Current IGBT compact models at Infineon are physics-based subcircuit representations in SPICE syntax. They were developed to run in the circuit simulator SIMetrix, and are manually calibrated. The aim of this work is to present advanced models for the micro-pattern trench IGBT implemented in Verilog-A language, addressing the challenges of compact models in terms of calibration accuracy, simulation run time, model robustness and portability to multiple simulators.

Fig. 3: IGBT technology overview showing schematically

the static excess-carrier density distribution in the plasma region.

[paper] Compact Modeling of IGBT

Y. Miyaoku, A. Tone, K. Matsuura, M. Miura-Mattausch, H. J. Mattausch, and *D. Ikoma

Compact Modeling of IGBT Charging/Discharging

for Accurate Switching Prediction

IEEE J-EDS,  DOI:10.1109/jeds.2020.3008919 

Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan

*Denso Corp., Aichi, Japan

Abstract: The trench-type IGBT is one of the major devices developed for very high-voltage applications, and has been widely used for the motor control of EVs as well as for power-supply systems. In the reported investigation, the accurate prediction of the power dissipation of IGBT circuits has been analyzed. The main focus is given on the carrier dynamics within the IGBTs during the switching-off phase. It is demonstrated that discharging and charging at the IGBT’s gate-bottom-overlap region, where electron discharging is followed by hole charging, has an important influence on the switching performance. In particular, the comparison of long-base and short-base IGBTs reveals, that a quicker formation of the neutral region within the resistive base region, as occurring in the long-base IGBT, leads to lower gatebottom-overlap capacitance, thus realizing faster electron discharging and hole charging of this overlap region.

Fig: Studied IGBT structure with indicated current flows

[paper] Compact Modeling of NC FDSOI FETs

C. K. Dabhi, S. S. Parihar, A. Dasgupta and Y. S. Chauhan

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

IEEE TED, vol. 67, no. 7, pp. 2710-2716, July 2020

DOI: 10.1109/TED.2020.2994018

Abstract: The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator– semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NCFDSOI model is computationallyefficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

Fig: (a) Schematic of NC MFIS FDSOI FET - FE layer is sandwiched between the oxide layer and the top gate. (b) Gate-stack of MFIS FDSOI FET. (c) Gate-stack of MFMIS FDSOI FET.

Acknowledgment: This work was supported in part by the Swarnajayanti Fellowship and FIST Scheme of the Department of Science and Technology and in part by the Berkeley Device Modeling Center (BDMC). The authors would like to thank Dr. Sarvesh S. Chauhan for reading the manuscript and providing valuable feedback.

[paper] First Principles Based Compact Model for 2D-Channel MOSFETs

Das, Biswapriyo, and Santanu Mahapatra

First Principles Based Compact Model for 2D-Channel MOSFETs

researchgate.net online publication

Abstract: We propose a generalized compact model for any two-dimensional material channel-based metal-oxide-semiconductor field-effect transistors. Unlike existing ones, the proposed model is first principles based and thus has ability to predict the circuit performance only using the crystallographic information of the channel material. It is ‘core’ in nature and developed following the industry-standard drift-diffusion formalism based ‘top-down’ hierarchy employing the FermiDirac statistics. We also implement the model in professional circuit simulator and good convergence is observed in 15-stage ring oscillator simulation.

Fig: Synopsis of the modeling framework. First, certain material specific parameters are extracted employing density functional theory computations and Hamiltonian calibration, which thereafter are used to develop the compact device model of the 2D-channel MOSFET using drift-diffusion formalism. The drain current and terminal charges obtained henceforth are used to implement digital circuits in commercial circuit simulator using its Verilog-AMS interface. 

[read more...]

[paper] Compact Model for SIS Josephson Junctions

A Compact Model for Superconductor-Insulator-Superconductor (SIS) Josephson Junctions

Shamiul Alam, Mohammad Adnan Jahangir and Ahmedullah Aziz, Member, IEEE

Department of Electrical Engineering and Computer Science

University of Tennessee, Knoxville, TN, USA

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2020.3002448

Abstract: We present a Verilog-A based compact model for the superconductor-insulator-superconductor (SIS) Josephson junction. The model can generate both hysteretic and non-hysteretic current-voltage (I-V) response for the SIS junctions utilizing the Stewart-McCumber damping parameter. We calibrate our model with different SIS samples and demonstrate accurate matching between the simulated and experimental results. We implement temperature effect on the energy gap and the critical current of the superconductor to explore the dynamic trends in device characteristics. We calculate the junction inductance and stored energy as functions of junction current and temperature. We simulate the read/write operations of an SIS junction based cryogenic memory cell to illustrate the usability of our model.

Fig: (a) Device structure of an SIS Josephson junction
(b) the RCSJ model of a Josephson junction.

[paper] InAs-OI-Si MOSFET Compact Model

S. K. Maity, A. Haque and S. Pandit

Charge-Based Compact Drain Current Modeling of InAs-OI-Si MOSFET 

Including Subband Energies and Band Nonparabolicity

in IEEE TED, vol. 67, no. 6, pp. 2282-2289, June 2020

doi: 10.1109/TED.2020.2984578

Abstract: In this article, we report a physics-based compact model of drain current for InAs-on-insulator MOSFETs. The quantum confinement effect has been incorporated in the proposed model by solving the 1-D Schrödinger–Poisson equations without using any empirical model parameter. The model accurately captures the variation of surface potential, charge density in the inversion layer, and subband energy levels with gate bias inside the quantum well. The conduction-band nonparabolicity effect on modification in eigen energy, effective mass, and density of states is derived and incorporated into the proposed model. The velocity overshoot effect that originates from the quasi-ballistic nature of carrier transport is also considered in the model. The proposed drain current model has been implemented in Verilog-A to use in the SPICE environment. The model predicted results are in good agreement with the commercial device simulator results and experimental data. 

Fig: Energy band profile of InAs-OI-Si MOSFET in the direction perpendicular to the oxide interface at flat-band condition. E0 and E1 denote the first and the second subband energy levels, respectively, and ΔEc and Vox represent the conduction-band offset between buffer-channel and oxide-channel regions, respectively.

Acknowledgment: The author S. Pandit would like to thank the Department of Electronics and Information Technology, Government of India for utilizing the resources obtained under the SMDP-C2SD Project at the University of Calcutta.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9067014&isnumber=9098120

[paper] reached 2000 reads at ResearchGate

Grabiński, Władysław, Daniel Tomaszewski, Laurent Lemaitre, and Andrzej Jakubowski

Standardization of the compact model coding: non-fully depleted SOI MOSFET example

Journal of Telecommunications and Information Technology (2005): 135-141.

Abstract - The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconduc-tor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, avail-ability, version control, verification and validation. Most com-pact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in par-ticular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC de-sign process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented. 

Fig: Approximation of the distribution of currents components

in the non-fully depleted SOI MOSFET.  

Keywords: Verilog-AMS, compact model coding, SOI MOSFET.

References:

1. ITRS Roadmap Update, 2003, http://www.public.itrs.net
2. Open Verilog International, "Verilog-AMS, Language Reference Manual", Version 1.9, 1999, http://www.accellera.org/
3. D. Tomaszewski, "Consistent DC and AC models of non-fully depleted SOI MOSFETS in strong inversion", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 111-114.
4. L. Lemaitre, C. McAndrew, and S. Hamm, "ADMS - automatic device model synthesizer", in Proc. IEEE CICC 2002, Florida, USA, 2002, pp. 27-30.
5. J. R. Hauser, "Small signal properties of field effect devices", IEEE Trans. Electron Dev., vol. 12, pp. 605-618, 1965.
6. D. Tomaszewski, "A small-signal model of SOI MOSFETs capacitances". Ph.D. thesis, Institute of Electron Technology, Warsaw, 1998.
7. L. Lemaitre, W. Grabiński, and C. McAndrew, "Compact device modeling using Verilog-A and ADMS", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 59-62.
8. C. Lallement, F. Pecheux, and W. Grabiński, "High level description of thermodynamical effects in the EKV 2.6 most model", in Proc. 9th Int. Conf. Mix.-Sig. Des. Integr. Cir. Syst. MIXDES, Wrocław, Poland, 2002, pp. 45-50.

EKV2.6 conference paper reached 50 reads

W. Grabinski et al., "FOSS EKV2.6 Verilog-A Compact MOSFET Model," 

ESSDERC, Krakow, Poland, 2019, pp. 190-193.

doi: 10.1109/ESSDERC.2019.8901822

[paper] Gallium Nitride FET Model

Gallium Nitride FET Model

V V Orlov, G I Zebrev

National Research Nuclear University MEPHI, Moscow, Russia

E-mail: gizebrev@mephi.ru

Abstract: We have presented an analytical physics-based compact model of GaN power FET, which can accurately describe the I-V characteristics in all operation modes. The model considers the source-drain resistance, different interface trap densities and self-heating effects. (read more 

https://arxiv.org/ftp/arxiv/papers/1909/1909.05702.pdf)

Introduction: Gallium nitride (GaN) high electron mobility transistor (HEMT) technology has many advantages, that make it a promising candidate for high-speed power electronics. It allows high-power operation at much higher frequencies than silicon laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs), currently a staple for the cellular base station industry [1]. The high breakdown voltage capability (over 100 V), high electron mobility, and high-temperature performance of GaN HEMTs are the main factors for its use in power electronics applications. Circuits design in both application regimes requires the accurate compact device models that can describe the non-linear I-V characteristics. The current state-of-the-art GaN power transistor circuit models are mostly empirical in nature and contain a large number of fitting parameters. The source-drain series resistance and self-heating make the compact modeling difficult [2]. Currently available models are not enough accurate to describe the I-V characteristics of power GaN HEMTs in all operation modes. This means, that we need a compact physics-based analytical model based on the physical description of the device. In this paper, we present a physics-based GaN power transistor model based on generic approach The paper contains 3 parts. In the first part, we will give a concise description of the model. The specific power HEMT’s effects, such as series resistance and self-heating will be discussed in the second and third parts 

[paper] Prediction of DC-AC Converter Efficiency Degradation

Kenshiro Sato, Dondee Navarro, Shinya Sekizaki, Yoshifumi Zoka, Naoto Yorino,
Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 

Prediction of DC-AC Converter Efficiency Degradation due to Device Aging
Using a Compact MOSFET-Aging Model

IEICE Transactions on Electronics

論文ID 2019ECP5010, [早期公開] 公開日 2019/09/02

Online ISSN 1745-1353, Print ISSN 0916-8524, https://doi.org/10.1587/transele.2019ECP5010,
https://www.jstage.jst.go.jp/article/transele/advpub/0/advpub_2019ECP5010/_article/-char/ja,

Abstract: The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.

An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model

Ravi Goel, Chetan Gupta, Yogesh S. Chauhan

EE Department, Indian Institute of Technology Kanpur, Kanpur, India

Published in: 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)

Abstract: Recent enhancement in BSIM-BULK (formerly BSIM6) model is presented in this work. The industry standard models like BSIM4, PSP, BSIM-BULK etc. lack the parameters for tuning of transconductance to channel current ratio (gm/Id). gm/Id is also a critical figure of merit for analog applications. Here, we propose an empirical model to enhance the flexibility of gm/Id tuning behavior. The proposed model provides good fitting for different channel lengths and drain bias.

Paper Sections:
I. Introduction
II. An Empirical Model for gm/Id Tuning
III. Model Implementation
IV. Model Validation with TCAD
V. Conclusion

Source:
DOI: 10.1109/UPCON.2018.8597065

A Guide to Creating Robust Device Models

Well-Posed Device Models for Electrical Circuit Simulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues.

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:

“NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/
https://nanohub.org/resources/26200/download/well-posed_device_models-29453e4.pdf

[paper] Artificial neural network design for compact modeling of generic transistors

Artificial neural network design for compact modeling of generic transistors

(J Comput Electron; pp. 1-8;  2017)

Lining Zhang and Mansun Chan

Department of ECE, Hong Kong University of Science and
Technology, Kowloon, Hong Kong

Abstract: A methodology to develop artificial neural network (ANN) models to quickly incorporate the characteristics of emerging devices for circuit simulation is described in this work. To improve the model accuracy, a current and voltage data preprocessing scheme is proposed to derive a minimum dataset to train the ANN model with sufficient accuracy. To select a proper network size, four guidelines are developed from the principles of two-layer network. With that, a reference ANN size is proposed as a generic three-terminal transistor model. The ANN model formulated using the proposed approach has been verified by physical device data. Both the device and circuit-level tests show that the ANN model can reproduce and predict various device and circuits with high accuracy [read more...]

(Published online April 9, 2017 http://dx.doi.org/10.1007/s10825-017-0984-9)