Jul 29, 2016

Optimization of CMOS-ISFET-Based Biomolecular Sensing: Analysis and Demonstration in DNA Detection https://t.co/t6fbc5xrR3 #papers


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July 29, 2016 at 10:25AM
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Jul 26, 2016

#papers #TINA: Creating Analog Components with #Verilog-A https://t.co/TGtUANqt6b


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July 26, 2016 at 01:44PM
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#nanoHub #papers: A Verilog-A Compact Model for Negative Capacitance FET https://t.co/m05FR5u0gR https://t.co/QpJoXZ3m98


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July 26, 2016 at 01:42PM
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ESOF 2016 - #EC #Research & #Innovation https://t.co/CENYnfTIhl #papers #openinnovation https://t.co/TwOJ8wntia


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ESOF 2016 - #EC #Research & #Innovation https://t.co/CENYnfTIhl #papers #openinnovation


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July 26, 2016 at 10:06AM
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Jul 25, 2016

FOSDEM 2017 - Next FOSDEM: 4 & 5 February 2017 https://t.co/xH7IAxXLyr #papers https://t.co/TlZzFKZVB9


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July 25, 2016 at 04:59PM
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FOSDEM 2017 - Next FOSDEM: 4 & 5 February 2017 https://t.co/xH7IAxXLyr #papers


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July 25, 2016 at 04:59PM
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Implementation and quality testing for HICUM/L2 compact models implemented in Verilog-A https://t.co/xXnNhTZcgb #papers


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July 25, 2016 at 02:11PM
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Jul 22, 2016

VeSFET is a twin-gate device with 3D vertical terminals and channel based on SOI conventional CMOS https://t.co/AGiySLvzUj #papers


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Jul 20, 2016

Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:
The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.


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Location: Grenoble, France

Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:
The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.


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Location: Grenoble, France

LETI Compact Modeling Links

LETI compact modeling links points to the Workshops and Conferences:

MOS-AK (Modeling of Systems and Parameter Extraction Working Group)
S3S (IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference)

IEDM (IEEE International Electron Devices Meeting)
VLSI  (29th International Conference on VLSI Design)
SISPAD (Simulation of Semiconductor Processes and Devices)

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Location: Grenoble, France

Jul 17, 2016

Simple Yet Effective ESD Testing Methods for Higher Reliability https://t.co/5CaZptRQQr #semi #papers


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July 17, 2016 at 01:08PM
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Jul 16, 2016

#Intel Adds Tsu-Jae #King #Liu, Taking Step Toward #Board Diversity https://t.co/vV9ndoVPtf #semi #feedly #papers


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July 16, 2016 at 05:52PM
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Jul 14, 2016

A flexible #memristive #model with simplex basis function https://t.co/iuavZ4S7Qc #papers


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July 14, 2016 at 02:19PM
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A flexible #memristive #model with simplex basis function https://t.co/iuavZ4S7Qc #papers


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July 14, 2016 at 02:19PM
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Jul 8, 2016

3year €33m European project REFERENCE to extend RF-SOI technology for above-1Gb/s 4G+ modules https://t.co/zlMd9QABXm #tech #feedly #papers


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July 08, 2016 at 11:34PM
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An improved model for substrate in RF SOI MOSFET varactor https://t.co/iK16GyX82y #papers #feedly


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[mos-ak] [2nd Announcement and Call for Papers] MOS-AK ESSDERC/ESSCIRC Workshop; Lausanne September 12, 2016

 MOS-AK ESSDERC/ESSCIRC Workshop  
  Lausanne September 12, 2016 
   2nd Announcement and Call for Papers  

 Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and local workshop coordinator Jean-Michel Sallese, EPFL (CH) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 14th consecutive MOS-AK ESSDERC/ESSCIRC Workshop which will be held at Swisstech Convention Centre in Lausanne on September 12, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
  • Call for Papers - June 2016
  • 2nd Announcement - July 2016
  • Final Workshop Program - August 2016
  • MOS-AK Workshop - Sept.12 2016
Venue:
Swisstech Convention Centre EPFL                                        
Route Louis-Favre 2
CH-1024 Ecublens

Topics to be covered include the following among other related to the compact/SPICE modeling :
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Speakers: tentative list of MOS-AK Experts:
  • Marco Bellini, ABB (CH)
  • Mike Brinson, LondonMet, (UK)
  • Matthias Bucher, TUC (GR)
  • Mansun Chan, UST (HK)
  • James Greer, ASCENT, Tyndall (IE)
  • Benjamin Iniguez, URV (SP)
  • Alexander Kloes, THM (D)
  • Muhammad Nawaz, ABB (SE)
  • Denis Rideau, ST (F)
  • Jean-Michel Sallese, EPFL (CH)
  • Andrei Vladimirescu, UCB (USA); ISEP (FR); Keynote
  • Lining Zhang, UST (HK)
Online MOS-AK Abstract Submission:
Prospective authors should submit an abstract to abstracts@mos-ak.org

Online Workshop Registration:
http://esscirc-essderc2016.epfl.ch/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee
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Location: Lausanne, Switzerland

Jul 6, 2016

"Measurement and analysis techniques for device agnostic electrical cha" #papers by James E Moore https://t.co/ryg6hgFn5f


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July 06, 2016 at 08:56AM
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Jul 1, 2016

Dual-Gate JFET #Modeling https://t.co/Cwroa516sK


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July 01, 2016 at 04:20PM
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Tutorial on Signal Processing in Linux with Octave https://t.co/Lzoeytzqwt #todo #feedly #papers


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July 01, 2016 at 08:13AM
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Jun 30, 2016

The #EAGLE has landed: at #Autodesk! #papers #opensource #kicad https://t.co/pKRvYSLMhd


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June 30, 2016 at 10:13AM
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TFT Small Signal Model and Analysis #DOMINO #papers https://t.co/NcRpCSjCQk


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June 30, 2016 at 10:05AM
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Jun 24, 2016

Is a Road To #5nm https://t.co/ks8mDGXr2g #papers


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June 24, 2016 at 09:27PM
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Large-Signal Verilog-A Model of Graphene Field-Effect Transistors #papers https://t.co/YvjUJBBp9n


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June 24, 2016 at 09:24PM
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Power Semiconductor Devices and Smart Power IC Technologies CFP https://t.co/1N4eQf5ufj #papers #feedly


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June 24, 2016 at 07:58PM
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#Science in #China https://t.co/dZfpCgzuVs #papers #feedly


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June 24, 2016 at 07:46PM
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Proposal of Physics-Based Equivalent Circuit of Pseudo-#MOSCap Structure for Impedance Spectroscopy https://t.co/yjZkpnrwQo #papers #feedly


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June 24, 2016 at 07:37PM
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#China #R&D by the numbers https://t.co/43JN3uARBC #papers #feedly https://t.co/s6vOoDT9ir


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June 24, 2016 at 07:35PM
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#China #R&D by the numbers https://t.co/43JN3uARBC #papers #feedly


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June 24, 2016 at 07:35PM
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Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits https://t.co/1gydKvYkKV #papers #feedly


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June 24, 2016 at 09:10AM
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Jun 21, 2016

Analysis and Performance Study of III–V Schottky Barrier Double-Gate MOSFETs Using a 2-D Analytical Model https://t.co/vLSMO52Cys #papers


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June 21, 2016 at 03:24PM
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Jun 18, 2016

New Y-function based MOSFET parameter extraction method from weak to strong inversion range https://t.co/qIhncY55c7 #papers #feedly


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June 18, 2016 at 09:13PM
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Jun 17, 2016

Organic Semiconductors Books to Download https://t.co/7ccToLje3o #papers


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June 17, 2016 at 09:37AM
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Jun 16, 2016

Near-Threshold Computing https://t.co/KUUFizDja3 #papers


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June 16, 2016 at 02:37PM
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A practical guide to SOI by Incize https://t.co/9JPT9AbwT1 #papers


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Jun 15, 2016

[mos-ak] [Final Program] International MOS-AK Workshop Shanghai June 26-28 2016

 International MOS-AK Workshop
 Shanghai, June 26-28, 2016
 The Final MOS-AK Workshop Technical Program

 Together with the MOS-AK Honorary Committee: Xi Wang (SIMIT), Tzu-Yin Chiu, (SMIC),  Ming-Kai Tsai, (MediaTek SRC/CMC), the Extended MOS-AK TPC Committee as well as local organizers Min Zhang (SIMTAC) and Eva Tu (SIMTAC), we have pleasure to invite to the MOS-AK Workshop which will be held in Shanghai between June 26-28, 2016. The MOS-AK workshop is organized with aim to strengthen an academic/industry network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. In addition, on June 26, 2016, dedicated compact modeling/characterization tutorial courses are also prepared for all workshop attendees.

Venue:   
865 Changning Road, Building No. 5, on the 3rd Floor, 
Conference Hall,
Changning District, Shanghai (CN)

Online Workshop Registration:
<http://www.simtac.org/?p=156&lang=zh>
(or contact MOS-AK Workshop Secretary: Eva Tu (Shanghai) <wanv.tu@simtac.org>)

The Workshop Agenda and its Program is available online:
<http://www.mos-ak.org/shanghai_2016/>
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)

Extended MOS-AK Committee

WG15062016
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[mos-ak] [Final Program] International MOS-AK Workshop in Shanghai on June 26-28, 2016

 International MOS-AK Workshop
 Shanghai, June 26-28, 2016
 The Final MOS-AK Workshop Technical Program

 Together with the MOS-AK Honorary Committee: Xi Wang (SIMIT), Tzu-Yin Chiu, (SMIC),  Ming-Kai Tsai, (MediaTek SRC/CMC), the Extended MOS-AK TPC Committee as well as local organizers Min Zhang (SIMTAC) and Eva Tu (SIMTAC), we have pleasure to invite to the MOS-AK Workshop which will be held in Shanghai between June 26-28, 2016. The MOS-AK workshop is organized with aim to strengthen an academic/industry network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. In addition, on June 26, 2016, dedicated compact modeling/characterization tutorial courses are also prepared for all workshop attendees.

Venue:   
865 Changning Road, Building No. 5, on the 3rd Floor, 
Conference Hall,
Changning District, Shanghai (CN)

Online Workshop Registration:
<http://www.simtac.org/?p=156&lang=zh>
(or contact MOS-AK Workshop Secretary: Eva Tu (Shanghai) <wanv.tu@simtac.org>)

The Workshop Agenda and its Program is available online:
<http://www.mos-ak.org/shanghai_2016/>
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)

Extended MOS-AK Committee

WG15062016
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[book] Compact Models for Integrated Circuit Design

 Compact Models for Integrated Circuit Design: 
 Conventional Transistors and Beyond
 Samar K. Saha
Taylor & Francis, 26 Aug 2015 - Technology & Engineering - 545 pages - ISBN 9781482240665

Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond provides a modern treatise on compact models for circuit computer-aided design (CAD). Written by an author with more than 25 years of industry experience in semiconductor processes, devices, and circuit CAD, and more than 10 years of academic experience in teaching compact modeling courses, this first-of-its-kind book on compact SPICE models for very-large-scale-integrated (VLSI) chip design offers a balanced presentation of compact modeling crucial for addressing current modeling challenges and understanding new models for emerging devices.
Starting from basic semiconductor physics and covering state-of-the-art device regimes from conventional micron to nanometer, this text:
  • Presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models
  • Discusses the major issue of process variability, which severely impacts device and circuit performance in advanced technologies and requires statistical compact models
  • Promotes further research of the evolution and development of compact models for VLSI circuit design and analysis
  • Supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices
  • Includes exercise problems at the end of each chapter and extensive references at the end of the book

Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond is intended for senior undergraduate and graduate courses in electrical and electronics engineering as well as for researchers and practitioners working in the area of electron devices. However, even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts from this book. [more...]
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Jun 13, 2016

Programme of the 4th Training Course on Compact Modeling

The 4th Training Course on Compact Modeling (TCCM) will take place in Tarragona (Catalonia, Spain) from June 27 to 28 2016.

The 4th TCCM is partially sponsored by the DOMINO EU H2020 project. It will consist a series of lectures conducted by prestigious researchers in the field of modeling of semiconductor devices, dealing with several issues related to the semiconductor device modeling, mostly compact/SPICE modeling. It is a very interesting event to PhD students and young researchers, but can interest senior researchers too. These lectures will be conducted by top experts in the field. 

No doubt the 4th TCCM will be useful to researchers working on compact modeling, but also to researchers working on circuit design, numerical modeling, device characterization and semiconductor device technology.

TCCM is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The General Chair of TCCM is Prof. Benjamin Iñiguez, who is also the Coordinator of the DOMINO project.

Programme of TCCM:

June 27 2016
8:30
Opening
Benjamin Iñiguez (Universitat Rovira i Virgili)
8:55
"Compact modeling for biological applications".
Morgan Madec (Université de Strasbourg, France)
10:05
"TCAD and semiclassical device modeling"
 Christoph Jungemann (RWTH-AAchen, Germany)
11:15
Coffe Break
11:40
"Modeling and experimental verification of mechanical stress effects in  ultra-thin Si MOSFET devices integrated into flexible packages. "
Heidrun Alus (AdMOS GmbH, Germany)
12:50
"Device simulation for Organic Electronics using GENIUS"
Heinz Olav Müller (Plastic Logic GmbH, Germany))
14:00
Lunch
15:15
"TCAD for compact model development"
Ahmed Nejim (Silvaco Europe Ltd. , UK)
16:25
"Modelling of Amorphous-Oxide-Semiconductors TFTs for large-area flexible electronics"
Fabrizio Torricelli (University of Brescia, Italy)
20:30
Gala Dinner


June 28 2016
8:45-14:00  Mini-Colloquium on Compact Modeling and Parameter Extraction
8:45
"An Integrated Approach for Circuit Performance and Reliability Simulation"
Mansun Chan (Hong Kong University of Science and Technology)
9:55
"Static and dynamic characterization of SiC based MOSFETs/IGBTs"
Muhammad Nawaz (ABB Sweden)
11:05
Coffee Break
11:30
“Model parameter extraction”
Antonio Cerdeira (CINVESTAV Mexico)
12:50
"Compact modeling for AlGaN/GaN HEMTs"
Benjamin Iñiguez (URV)
14:00
Lunch
15:15
"Application of compact models for organic circuit design"
Eugenio Cantatore (TU-Eindhoven, The Netherlands)
16:25
« Mathematical and Semi-physical compact modeling for emerging technologies”
Firas Mohamed (Infiniscale, France)
17:35
End of the Training Course

Besides, on June 29 1016, the  Workshop on Flexible Electronics (WFE) will take place in Tarragona, too. Attendees to TCCM who work on Flexible Electronics (not necessarily modeling) will have a chance to present recent results on their own. But WFE is open to all researchers.


Registration to both events is open. It is possible to register only to TCCM, or only to WFE or to both. It is quite cheap, in partular for students, and includes lunches, coffee breaks, and in the case of TCCM, a gala dinner.

Finally, on June 30-July 1 the Annual Graduate Student Meeting on Electronic Engineering will be held, consisting of plenary talks by prestigious researchers and student presentations. Registration is free.



I encourage researchers on semiconductor devices and circuit design to attend TCCM!

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