[paper] Characterization of ultrathin FDSOI devices using subthreshold slope method

Teimuraz Mchedlidze¹, and Elke Erben²

Characterization of ultrathin FDSOI devices using subthreshold slope method

Phys. Status Solidi A. Accepted Manuscript

DOI: 10.1002/pssa.202000625

1 TU Dresden, Germany

2 Globalfoundries, Dresden, Germany

Abstract: The subthreshold current-voltage (subthreshold slope) characteristic of fully depleted silicon-on-insulator high-k dielectric-metal gate field-effect transistor is applied for evaluation of the interface traps located at both, the front and back channels. The proposed characterization method allows an estimation of averaged trap densities separately for the front and the back interfaces of the channel. Performing subthreshold slope measurements at several temperatures allow the extraction of the energy distributions of the interface trap densities for both interfaces and obtaining essential characteristics of the stack.

Fig: Results of ID(VGF,k,T) measurements for EG sample. At each temperature 

(200, 300 and 400K) a group of curves contains data for eight k values

(k = 0 to 3 with step 0.5 and kOC; solid curve). 

Acknowledgements: The authors would like to acknowledge funding of the study in the frames of the IPCEI WIN- FDSOI project from Global Foundries. We want to thank Jörg Weber (TU Dresden), Luca Pirro (Global Foundries) and Rolf Öttking (AQ Computare, Chemnitz) for thoughtful discussions and suggestions.

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[paper] Compact Model for Power MOSFET

Abdelghafour Galadi

PSPICE compact model for power MOSFET based on manufacturer datasheet

DOI:10.1088/1757-899X/948/1/012007

National School of Applied Sciences of Safi, Cadi Ayyad University, Marrakech (MA)

Abstract: In this paper, large signal model for power MOSFET devices is presented. The proposed model includes quasi-saturation effect and describes accurately the electrical behavior of the power MOSFET devices. The large signal model elements will be provided based on the device structure. Furthermore, the model parameters are extracted from measurements considering the voltages depending effect of the nonlinear gate-source, gate-drain and drain-source interelectrode capacitances. Excellent agreements will be shown between the simulated and the datasheet data. Finally, a description of the model will be provided along with the parameter extraction procedure.

Fig: a) Conventional power MOSFET structure with b) its subcircuit elements. 

[paper] HEMT RF/Analog Performance

M. Khaouani¹,H. Bencherif², A. Hamdoune¹, A. Belarbi³, Z. Kourdi⁴

RF/analog Performance Assessment of High Frequency, Low Power In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7As HEMT Under High Temperature Effect

Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers 2020

DOI: 10.1007/s42341-020-00250-8

1 Department of Genie Electric and Electronics, Unit Research of Material and Renewable Energies, University Aboubek Belkaid, Tlemcen, Algeria
2 LAAAS Laboratory, University of Batna 2, Batna, Algeria
3 Center Exploitation Telecommunication Satellite– Bouchaoui-Alger, Algeria Space Agency, Algiers, Algeria
4 Center Exploitation Telecommunication Satellite– Oran-Alger, Algeria Space Agency, Algiers, Algeria

In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7As In this paper, we performed a Pseudo-morphic High Electron Mobility Transistors (pHEMT) In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7As using commercial TCAD. RF and analog electrical characteristics are assessed under high temperature effect. The impact of the temperature is evaluated referring to a device at room temperature. In particular, the threshold voltage (Vth), transconductance (gm), and Ion/Ioff ratio are calculated in the temperature range of 300K to 700K. The primary device exhibits a drain current of 950mA, a Vth of -1.75V, a high value of gm of 650 mS/mm, Ion/Ioff ratio of 1E6, a transition frequency (fT) of 790GHz, and a maximum frequency (fmax) of 1.4THz. The achieved results show that increasing temperature act to decrease current, reduce gm, and Ion/Ioff ratio. In more detail high temperature causes a phonon scattering mechanism happening that determine in turn a reduced drain current and shift positively the threshold voltage resulting in hindering the device DC/AC capability. 

Fig: 2D cross section of In_0.3Al_0.7As/InAs/InSb/In_0.3Al_0.7AsAs PHEMT