Feb 23, 2018

[Short Course] RFSOI: from basics to practical use of wireless technology

RFSOI: from basics to practical use of wireless technology

18th of March, Granada, Spain
LLN
  
Incize organizes a one-day short course at EuroSOI-ULIS about Silicon-on-Insulator (SOI) technology for RF applications. The tutorial is given by globally recognized experts in the field. It aims to provide its participants with the knowledge about SOI materials, devices, circuits and performance.

  
The Silicon-on-Insulator (SOI) technology is gaining more grounds in the domains of RF applications. Nearly 100% of RF antenna switches in wireless system Front-End Modules (FEM) are based on SOI. A FEM entirely built on SOI can be implemented in the observable future as both academia and industry are working in this direction.

  
This tutorial will be of interest for engineers and graduate students willing to prepare themselves for the future RF applications.

Program:Sunday, March 18
08:00 – 08:50RF SOI, fabrication, materials and eco-system
(Abstract)
Ionut Radu
Director of Advanced R&D
Soitec, France
Ionut Radu
08:50 – 09:40Fundamentals of RF SOI technology(Abstract)Jean-Pierre Raskin
Professor
UCL, Belgium
Jean-Pierre
09:40 – 10:10Break
10:10 – 11:0022nm FDSOI Technology optimized 
for RF/mmWave Applications
 (Abstract)
David L. Harame
RF CTO Development and Enablement
GlobalFoundries, Germany
David L. Harame
11:00 – 11:50RF SOI technology and components for 5G connectivityChristine Raynaud
Program Manager (Business Development – Technology to Design)
CEA-Leti, France
Christine Raynaud
11:50 – 13:30Lunch
13:30 – 14:20Analog and RF design on SOI (Abstract)Barend van Liempd
Senior Researcher
imec, Belgium
Barend van Liempd
14:20 – 15:10Techniques and tricks for RF measurements on SOI Andrej Rumiantsev
Director RF Technologies
MPI Corporation, Germany
Andrej Rumiantsev
15:10 – 15:40Break
15:40 – 16:30FOSS TCAD/EDA tools for advanced 
SOI-device modeling
 (Abstract)
Wladek Grabinski
R&D CM Manager
MOS-AK, Switzerland
Wladek Grabinski
16:30 – 17:20RF design flow for SOIIan Dennison
Design Systems Senior Group Director
Cadence, UK
Ian Dennison


To register, please use the EuroSOI-ULIS registration website

More information about the EuroSOI-ULIS conference and the technical Program


For any inquiries please email us at info@incize.com
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Feb 22, 2018

[paper] TFET Devices Re-Evaluation Résumé

Capturing Performance Limiting Effects in Tunnel-FETs
Michael Graef1,2, Fabian Hosenfeld1,2, Fabian Horst1,2, Atieh Farokhnejad1,2
Benjamín Iñíguez2 and Alexander Kloes1
1Competence Centre for Nanotechnology and Photonics, THM, Giessen, Germany
2DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
ISTE OpenScience DOI: 10.21494/ISTE.OP.2018.0220

Abstract: In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior of the TFET is shown. In focus of this work are the emerging variability issues with this new type of device. Random-dopant-fluctuations (rdf) have a major influence on the device performance. This effect is analyzed and compared with rdf effects in a MOSFET device. The drawn conclusions lead to a re-evaluation of performance limiting aspects of fabricated TFET devices [read more: 10.21494/ISTE.OP.2018.0220]

 FIG: a) Schematic geometry of an n-type DG Tunnel-FET, showing its structural parameters and doping profiles. b) Schematic band structure of a n-Tunnel-FET showing the different operating regimes and their dominating currents. 


[paper submission] MIXDES 2018


This year the 25th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2018 will take place on June 21-23, 2018 in Gdynia, Poland

Submit a paper <https://www.mixdes.org/Mixdes3/>

Feb 21, 2018

#NEST is a simulator for spiking neural network #model https://t.co/BZaG7UkZXD https://t.co/0yGf5g7nNJ


from Twitter https://twitter.com/wladek60

February 21, 2018 at 08:33PM
via IFTTT

[paper] Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy Based on EKV3.0 Model

Amine AYED and Hamadi GHARIANI
LETI Laboratory-ENIS
Sfax, Tunisia
IJACSA Vol. 8, No. 12, 2017

Abstract—In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz [read more...]

Fig.: Eye diagram for a VCO output @ 433MHz


Feb 8, 2018

Today in Tech - 1956 - Douglas “Doug” Ross is best known to have originated the term “CAD” https://t.co/xO2K99dn7i #model


from Twitter https://twitter.com/wladek60

February 08, 2018 at 10:20PM
via IFTTT

BSIM3v3 to EKV2.6 Model Parameter Extraction

BSIM3v3 to EKV2.6 Model Parameter Extraction and Optimisation
using LM Algorithm on 0.18um Technology node
Kirmender Singh and Piyush Jain
Int. Journal of Electronics and Telecommunications 2018 Vol.64 No.1 pp.5-11

Abstract: The industry standard BSIM3v3 and BSIM4.0 have been replaced by BSIM6.0 compact MOSFET model for deep submicron technology node. The BSIM6.0 is next generation, defacto industry standard model for bulk MOSFET. This model is charge based which is continuous from weak to strong inversion of operation. The core of analytical and physical BSIM6 model[3] is charge, with drain current equation expressed in form of source (qs) and drain charge (qd). This model has all its governing equations continuous and can be used to develop design methodology using IC based approach. But its method of computing qs and qd is complicated which is different from Vittoz traditional charge calculation method. The continuous interpolation equation of drain current as adopted by EKV2.6 although is empirical but its compact expression is preferred by analog designer to get intuitive design guidance. BSIM6 is a combined effort by BSIM and EKV modeling groups based on charge based continuous equations. Although EKV2.6 model is not valid for deep submicron process as it only includes submicron short channel effects like velocity saturation (VS), vertical field mobility reduction (VFMR), Drain induced barrier lowering (DIBL), channel length modulation (CLM) etc. But it still offers some benefits to have first cut design methodology because of its much simplified analytical equations. The inversion coefficient (IC) has found extensive acceptance in designer community as it offers enhanced design elegance in EKV then more complicated BSIM model. This paper discuses first step in analog design process by extracted core EKV2.6 intrinsic model parameters from industry standard BSIM3v3 model on 0.18µ technology node. The 0.18µ technology is chosen as it is still more common technology node in analog circuit design. The model parameters are extracted for different bins and optimisation is done using nonlinear optimisation LM algorithm. The optimised EKV2.6 parameters are validated with currentvoltage(I-V), intrinsic voltage gain (Avi) and Early voltage circuit parameter (VA) with BSIM3v3 model [read more...]

Flow-chart of BSIM to EKV conversion steps
(source:
D. Stefanovic and M. Kayal “Structured Analog CMOS Design" Springer Publications, 2008)

Meet #India’s women #opensource warriors https://t.co/OmYxPwCdlg https://t.co/KdqUF66d4E


from Twitter https://twitter.com/wladek60

February 08, 2018 at 02:56PM
via IFTTT

ASAP7 predictive design kit development and cell design technology co-optimization: V. Vashishtha, M. Vangala and L. T. Clark, Invited #paper ICCAD, Irvine, CA, 2017 https://t.co/DS9MHtX5H4


from Twitter https://twitter.com/wladek60

February 08, 2018 at 02:01PM
via IFTTT

Feb 3, 2018

Assessing the impact of temperature and voltage variations in near-threshold circuits using an analytical #model... https://t.co/8wb8YJas8V


from Twitter https://twitter.com/wladek60

February 03, 2018 at 11:45AM
via IFTTT

Assessing the impact of temperature and voltage variations in near-threshold circuits using an analytical #model https://t.co/t0nkAEKBcw https://t.co/Av6FzcFvip


from Twitter https://twitter.com/wladek60

February 03, 2018 at 11:45AM
via IFTTT

Feb 1, 2018

F. Rasheed, M. S. Golanbari, G. Cadilha Marques, M. B. Tahoori and J. Aghassi-Hagmann, "A Smooth EKV-Based DC #Model for Accurate Simulation of Printed Transistors and Their Process Variations," in IEEE TED, vol. 65, no. 2, pp. 667-673, Feb. 2018.https://t.co/vQ0xogjSx4


from Twitter https://twitter.com/wladek60

February 01, 2018 at 07:56PM
via IFTTT

Jan 28, 2018

[PhD] Modeling and Spice Implementation of SOI G4FET

Modeling and Spice Implementation of Silicon on Insulator (SOI)
Four Gate (G4FET) Transistor
Md Sakib Hasan
PhD Dissertation
The University of Tennessee, Knoxville, August 2017

Abstract: As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology.
The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation.
The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET [read more...]

Jan 27, 2018

#C4P for a Special Issue of IEEE Transactions on Electron Devices on #2D #Materials for Electronic, Optoelectronic and Sensor Devices https://t.co/c76nBVISRO #paper


from Twitter https://twitter.com/wladek60

January 27, 2018 at 12:14AM
via IFTTT

Jan 26, 2018

X. Cheng, S. Lee and A. Nathan, "Deep #Subthreshold #TFT Operation and Design Window for #Analog Gain Stages," in IEEE JEDS, vol. 6, no. 1, pp. 195-200, 2018. 10.1109/JEDS.2018.2789579 https://t.co/tsvLTC9z0r #paper


from Twitter https://twitter.com/wladek60

January 26, 2018 at 08:23PM
via IFTTT

Jan 18, 2018

New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs https://t.co/7ZXUlR4MMk #paper


from Twitter https://twitter.com/wladek60

January 18, 2018 at 04:07PM
via IFTTT

[mos-ak] [2nd Announcement and Call for Papers] Spring'18 MOS-AK Workshop Strasbourg, March 15-16, 2018

Spring'18 MOS-AK Workshop
Strasbourg, March 15-16, 2018

2nd Announcement and Call for Papers 

Together with local organization team: Christophe Lallement and Morgan Madec (ESP, Uni Strasbourg), Technical MOS-AK Program Coordinator: Jean-Michel Sallese (EPFL) as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized at Strasbourg University on March 15-16, 2018

Planned, Spring MOS-AK/Strasbourg workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue: 
ICube Laboratory 
(UMR CNRS/UdS 7357)
Strasbourg University

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Dec. 2017
  • 2nd Announcement - Jan. 2018
  • Final Workshop Program - Feb. 2018
  • MOS-AK Workshop - March 15-16, 2018 
Prospective authors should 
submit abstract online
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Jan 14, 2018

Jan 10, 2018

Why isn't #opensource hot among computer science students? https://t.co/hynyL0FNam


from Twitter https://twitter.com/wladek60

January 10, 2018 at 09:43PM
via IFTTT

Dec 30, 2017

The Essential #OpenSource Reading List: 21 Must-Read #Books https://t.co/Xxw3AyMNPf Shared from my Google feed


from Twitter https://twitter.com/wladek60

December 30, 2017 at 12:02PM
via IFTTT