Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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Oct 25, 2017
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP
from Twitter https://twitter.com/wladek60
October 25, 2017 at 11:59AM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:59AM
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A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper
A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper
— Wladek Grabinski (@wladek60) October 25, 2017
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October 25, 2017 at 11:34AM
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Oct 24, 2017
Cryogenic characterization of CMOS technologies
A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz
Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing
47th ESSDERC, Leuven, Belgium, 2017, pp. 62-65.
Abstract: This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems [read more...] doi: 10.1109/ESSDERC.2017.8066592
R. M. Incandela, L. Song, H. A. R. Homulle, F. Sebastiano, E. Charbon and A. Vladimirescu
Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures
47th ESSDERC, Leuven, Belgium, 2017, pp. 58-61.
Abstract: The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK [read more...] doi: 10.1109/ESSDERC.2017.8066591
Oct 19, 2017
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE https://t.co/RZqPRisbbS
#opensource Summit Europe 2017 https://t.co/c1TgRIgzVE http://pic.twitter.com/RZqPRisbbS
— Wladek Grabinski (@wladek60) October 18, 2017
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October 18, 2017 at 11:41PM
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Oct 17, 2017
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
A Compact QS Terminal Charge and Drain Current #Model for DG Junctionless Transistors and Its Circuit Validation https://t.co/hTsw5blL8f
— Wladek Grabinski (@wladek60) October 17, 2017
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October 17, 2017 at 11:26AM
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[paper] Accurate diode behavioral model with reverse recovery
Stanislav Banáša,b, Jan Divínab, Josef Dobešb, Václav Paňkoa
aON Semiconductor, SCG Czech Design Center, Department of Design System Technology, 1. maje 2594, 756 61 Roznov pod Radhostem, Czech Republic
bCzech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka 2, 166 27 Prague 6, Czech Republic
Volume 139, January 2018, Pages 31–38
Highlights:
ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]
- The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
- Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
- The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
- Two methods of model parameter extraction or model validation have been demonstrated.
ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]
FIG: Solving the recursive calculation of reverse recovery charge
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