Jun 22, 2017
Rising SOI tide lifts Soitec into profit
https://shar.es/1BtAZy
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Jun 14, 2017
[C4P] IEDM 2017
The Annual International Electron Devices Meeting will be held at the Hilton San Francisco Union Square San Francisco, CA December 2-6, 2017
Abstract Deadline (four page final paper): August 2nd, 2017
A Call for Papers flyer is available here: IEDM 2017 Call For Papers.
Customized Call for Papers for each of the technical subcommittee areas are also available:
- Circuit and Device Interaction (CDI)
- Characterization, Reliability, and Yield (CRY)
- Compound Semiconductor and High Speed Devices (CHS)
- Memory Technology (MT)
- Modeling and Simulation (MS)
- Material and interface modeling
- Compact models
- Kinetic Monte Carlo and Molecular Dynamics
- Reliability and variability modeling
- Technology benchmarking
New or trending areas include: - First principle based quantum transport
- Process simulation with atomistic methods
- Self heating, interconnect and packaging
- Nano Device Technology (NDT)
- Optoelectronics, Displays, and Imagers (ODI)
- Power Devices (PD)
- Process and Manufacturing Technology (PMT)
- Sensors, MEMS, and BioMEMS (SMB)
[paper] Well-Posed Device Models for Electrical Circuit Simulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017
NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.
NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”
1For more information about NEEDS please visit https://nanohub.org/groups/needs/.
Jun 13, 2017
[mos-ak] [Workshop Program] 2nd Sino MOS-AK Workshop in Hangzhou June 29-30, 2017
Hangzhou June 29-30, 2017
Workshop Program online http://www.mos-ak.org/
Together with the Honorary Committee Chair LingLing Sun, HangZhou Dianzi University and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as the local coordinator Min Zhang, XMOD (Shanghai) and all the Extended MOS-AK TPC Members, we have pleasure to invite to the 2nd Sino MOS-AK Workshop in Hangzhou on June 29-30, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
- 2nd Announcement - April 2017
- Final Workshop Program - June 2017
- 2nd Sino MOS-AK Workshop - June 29-30, 2017
会议场所:杭州电子科技大学科技馆
Hangzhou Dianzi University; Science & Technology Museum
http://www.mos-ak.org/hangzhou_2017/
http://www.xmodtech.cn/Agenda (local link)
Note:
Above topic and time arrangement sequence could be with tiny variation due to presenter's personal reason
(演讲顺序可能有改变,敬请留意)
Online MOS-AK/Hangzhou Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
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May 16, 2017
Working Student in Power Management (Intel Munich)
Your main tasks in this full time position will be to:
- Setup a new framework to manage the power data in a new tool and environment
- Migrate existing project power consumption specifications and measurements currently in Excel
- Measure and correlate power KPIs on engineering samples in the post-silicon lab.
- Validate current power modelling approach and propose further model optimizations
- Contribute to the reporting and documentation for other teams and management
[read more...]
May 15, 2017
A Guide to Creating Robust Device Models
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017
1For more information about NEEDS please visit https://nanohub.org/groups/needs/
https://nanohub.org/resources/26200/download/well-posed_device_models-29453e4.pdf
Apr 25, 2017
[mos-ak] [C4P] IJHSES / MOS-AK Special Issue
The IJHSES Call for Papers
Special Issue on Advances in the Compact/SPICE Modeling
and its Verilog-A Standardization
Compact/SPICE models for circuit level simulation are essential element of supporting CAD/EDA tools for advanced integrated circuit designs. Rapid mainstream CMOS technology expansion and its scaling into the nanometer regime demands development of a fully physical as well as technology predictive compact/SPICE models for circuit simulation which provides adequate, full range DC, AC, RF, and noise characteristics and its geometry, bias, temperature scaling. These tasks becomes a major R&D challenge. Fast new technology nodes developments also impose new challenges on the compact/SPICE models maintenance and development as well as on its Verilog-A standardization for the model implementation, validation and dissemination.
Standard, core compact models should include and update noise/mismatch and reliability/variability models as well as proximity effects to adequately model nanoscale devices and technologies including nonclassical MOSFETs, multigate FinFETs and nanowire FETs partially/fully-depleted ultra thin body (UTB) SOI, and thin-film transistors (TFTs). High-frequency, high-voltage high-power, high-temperature devices have been extensively investigated, and their compact models to be reviewed, too. Heterogeneous integration opens a new perspectives to the CMOS platform to integrate different materials (III-V/Ge channel, organic and different source/drain injection mechanisms (Schottky-barrier, tunneling, junctionless FETs, and others) and new nonclassical devices, high GHz/THz range detectors, Bio/Med sensors, actuators, MEMS, among others, to support emerging device in future VLSI, IoT applications and beyond.
Therefore, there is an emerging need for an new special issue to review status, challenge and advancement in the compact/SPICE modeling for nanoscaled and emerging technologies as well as beyond. The IJHSES Editors seek original manuscripts for a special issue on advanced in the Compact/SPICE Modeling and its Verilog-A standardization.
Topics to be covered include the following, but are not limited to:
Advances in semiconductor technologies and processing
Compact Modeling (CM) of the electron devices
Verilog-A language for CM standardization
New CM techniques and extraction software
FOSS TCAD/EDA modeling and simulation
CM of passive, active, sensors and actuators
Emerging Devices, TFT CMOS and SOI-based memory cells
Organic, Bio/Med devices/technology modeling
Microwave, RF device modeling, HV/Power device modeling
Nanoscale CMOS devices and circuits
Technology R&D, DFY, DFT and IC Designs
Foundry/Fabless Interface Strategies
Paper Submission and Review Schedule:
First call for papers: April 2017
Second announcement: June 2017
Special Issue Due: Dec. 2017
IJHSES Editor-in-Chief | Co-Editors-in-Chiefs | Guest Editors |
Michael Shur Rensselaer Polytechnic Institute (USA) | Wladek Grabinski MOS-AK Association (EU) Benjamin Iñiguez DEEEA, ETSE, URV (SP) | Jean-Michel Sallese EPFL Lausanne (CH) Daniel Tomaszewski ITE Warsaw (PL) |
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