SANTA CLARA, Calif., Feb. 21, 2012
Agilent Technologies Inc. (NYSE: A) today announced that Accelicon Technologies' software solutions and technology for device-level modeling and validation in the electronics industry are now part of Agilent. The two companies had announced an acquisition agreement on Dec. 1, 2011. Financial details were not disclosed.
The acquisition, led by Agilent's EEsof EDA organization, further enhances Agilent's leadership in semiconductor device modeling. Accurate, verified device models are critical to reduce R&D design cycles as higher frequencies, smaller technology nodes, new materials and device layouts call for more accurate process design kits. As part of the Software and Modular Solutions Division, Agilent EEsof continues to integrate its industry-leading design simulation with real measurements to improve design efficiency for engineers who develop communications systems. These improved tools and processes solve the increasing complexities they face when designing communications systems for aerospace/defense and commercial wireless applications.
Agilent's newly acquired solutions from Accelicon include MBP for device-level extraction and model generation, MQA for device-level model validation and AMA for advanced model analysis, including layout effects.
Accelicon was founded in 2002 by noted industry veteran Dr. Xisheng Zhang, who has now joined Agilent along with former Accelicon CEO Tim K. Smith. The majority of the former Accelicon employees are located in Beijing; they are also now part of Agilent.
Feb 28, 2012
Feb 23, 2012
8th International Conference on Organic Electronics
Tarragona, Spain June 25‐27, 2012
Organic electronics is a rapidly growing technology that is anticipated to compare with conventional microelectronics in the near future to make transistor circuits, displays and solar cells. Other application like sensors are expected. The International Conference on Organic Electronics was held from 2005 to 2008 in Eindhoven, The Netherlands. In 2009, ICOE moved to Liverpool, United Kingdom, in 2010 to Paris, in 2011 in Rome, while the 2012 edition will be held at the campus of University Rovira i Virgili (URV) in Tarragona, Spain. The conference intends to cover all aspects of organic electronics, including materials and chemistry, transistors, OLEDs, photovoltaic cells, circuits and circuit design, manufacturing and inclusion in systems.
Technical areas include, but are not limited to:
- Materials and chemistry
- Transistors
- OLEDs Photovoltaic cells
- Circuits and circuit design
- Manufacturing and inclusion in systems
- Modelling
The conference will be held in coordination with two other events, partially related to the topic: the 10th Graduate Student Meeting on Electronic Engineering (June 21-22) and the 2nd International Training Course on Compact Modelling (TCCM 2012) (June 28-29).
Feb 20, 2012
[mos-ak] Final Program MOS-AK/GSA India Workshop on March 16-18, 2012
Final Program MOS-AK/GSA India Workshop on March 16-18, 2012
============================================================
http://www.mos-ak.org/india/
============================================================
http://www.mos-ak.org/india/
* Venue:
========
Jaypee Institute of Information Technology (JIIT),
A-10, Sector-62, Noida (U.P.), India
Phone: 0120-2400973-976, 2400987
http://www.mos-ak.org/india/#Venue
* Workshop Registration Form
============================
http://inae.org/contents/Registration%20Form.pdf
* Agenda:
=========
http://www.mos-ak.org/india/
with CMOS technology and SPICE Models Tutorial by Dr. N.D. Arora,
Silterra, Malaysia
Organizing MOS-AK/GSA Committee:
================================
A.B. Bhattacharyya, Emeritus Professor, JIIT, India (Chair)
S.C. Saxena, Vice Chancellor, JIIT, Noida (Host)
Ehrenfried Seebacher, austriamicrosystems AG, Austria (Co-Chair)
Wladek Grabinski, MOS-AK (European Arrangements Co-Chair)
M.J. Zarabi, Chairman, Vice-President, Microelectronics Forum INAE New
Delhi, India
Varambally Rajamohan, ST Microelectronics, India
Shantanu Mahapatra, IISc, India
Rajamohan Varambally, ST Microelectronics, Noida, India
Kulbhushan Misri, Freescale, Noida, India
M. Jagdesh Kumar, IIT Delhi, India
Manoj Saxena, Delhi University, South Campus, New Delhi, India
Extended MOS-AK/GSA Committee:
==============================
http://www.mos-ak.org/committee.html
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2nd Training Course on Compact Modeling
Building on the success of its first edition in 2012, the 2nd Training Course on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 28-29 2012. It will be organized by will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona).. The General Chairman is Prof. Benjamin Iñiguez.
The Training Course on Compact Modeling will consist of 12 of lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.
The final programme will be published very soon. Registration will be cheap. It will include lunches, coffe breaks and a Gala Dinner on June 28, in a nice restaurant with TV screens to watch the Semifinals match of the Soccer European Cup ...
Besides, on June 25-27 the same group at URV will organize 8th International Conference on Organic Electronics (ICOE 2012) also in Tarragona. Participants to this Training Course will have a reduced fee for ICOE 2012.
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (its Roman name) was one of the most important cities in the Roman Empire.
On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Speaking about Tarraco's climate, the famous Roman poet Virgil wrote: "The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring." Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.
I strongly encourage all people interested in compact modeling to attend the 2nd Training Course on Compact Modeling!
The Training Course on Compact Modeling will consist of 12 of lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.
The final programme will be published very soon. Registration will be cheap. It will include lunches, coffe breaks and a Gala Dinner on June 28, in a nice restaurant with TV screens to watch the Semifinals match of the Soccer European Cup ...
Besides, on June 25-27 the same group at URV will organize 8th International Conference on Organic Electronics (ICOE 2012) also in Tarragona. Participants to this Training Course will have a reduced fee for ICOE 2012.
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (its Roman name) was one of the most important cities in the Roman Empire.
On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Speaking about Tarraco's climate, the famous Roman poet Virgil wrote: "The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring." Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.
I strongly encourage all people interested in compact modeling to attend the 2nd Training Course on Compact Modeling!
8th International Conference on Organic Electronics
The 8th International Conference on Organic Electronics (ICOE 2012) will be held in Tarragona (Catalonia, Spain) on June 25-27 2012. ICOE'12 will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona). Prof. Benjamin Iñiguez will be the General Chairman of ICOE 2012.
The conference covers all aspects of organic electronics, including materials and chemistry, transistors (OTFTs), OLEDs, photovoltaic cells, circuits and circuit design, manufacturing and inclusion in systems.
"Modeling" is one of the topics, and of course, it includes Compact Modeling.
DEADLINE FOR A 2-PAGE ABSTRACT SUBMISSION: MARCH 1 2012.
The venue is the "Aula Magna" in one of the campuses of University Rovira i Virgili (URV) in Tarragona.
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (its Roman name) was one of the most important cities in the Roman Empire.
On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Speaking about Tarraco's climate, the famous Roman poet Virgil wrote: "The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring." Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.
A Gala Dinner will take place in the evening of June 26. I recommend atttendees to go; there will be no match of the Soccer European Cup on that date, so you will have something to enjoy...
Besides, on June 28-29 (just after ICOE 2012), the 2nd Training Course on Compact Modeling will be held also in Tarragona, organized by the same group at the Universitat Rovira i Virgili. ICOE participants will have a reduced fee for that Training Course, which will target many topics related to compact device modeling.
I encourage researchers working on Organic Electronics, including modeling to submit abstracts to ICOE'12.
The conference covers all aspects of organic electronics, including materials and chemistry, transistors (OTFTs), OLEDs, photovoltaic cells, circuits and circuit design, manufacturing and inclusion in systems.
"Modeling" is one of the topics, and of course, it includes Compact Modeling.
DEADLINE FOR A 2-PAGE ABSTRACT SUBMISSION: MARCH 1 2012.
The venue is the "Aula Magna" in one of the campuses of University Rovira i Virgili (URV) in Tarragona.
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (its Roman name) was one of the most important cities in the Roman Empire.
On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site.
Tarragona can be easily reached from Barcelona Airport by bus and train. It is about 100 Km South from Barcelona. Besides, Reus Airport (less than 15 Km from Tarragona) receives flights from many European cities in the summer.
Speaking about Tarraco's climate, the famous Roman poet Virgil wrote: "The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring." Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.
A Gala Dinner will take place in the evening of June 26. I recommend atttendees to go; there will be no match of the Soccer European Cup on that date, so you will have something to enjoy...
Besides, on June 28-29 (just after ICOE 2012), the 2nd Training Course on Compact Modeling will be held also in Tarragona, organized by the same group at the Universitat Rovira i Virgili. ICOE participants will have a reduced fee for that Training Course, which will target many topics related to compact device modeling.
I encourage researchers working on Organic Electronics, including modeling to submit abstracts to ICOE'12.
Feb 15, 2012
SMACD-2012
The International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) will be held in Seville (Spain) in September 2012 as a dedicated forum devoted to Design Methods and Tools for Analog, Mixed-signal, RF (AMS/RF) and multi-domain (MEMs, nanoelectronic, optoelectronic, biological, etc.) integrated circuits and systems.
SMACD 2012 topics of interest include, but are not limited, to:
• Performance modeling
• Power and thermal modeling
• Reliability modeling
• Variability modeling
• Compact device and circuit modeling
• Multi-domain modeling (optoelectronics, MEMs, biological, biochemical, etc.)
• Modeling languages and applications
• Linear and non-linear model reduction
• Circuit and system theory and applications
• Behavioral modeling and simulation
• Numerical and symbolic simulation methods
• Distributed and parallel circuit simulation
• Analysis and simulation techniques for emerging nanoscale devices
• Analysis of reliability effects: aging, electro-migration, BTI, etc.
• Simulation and estimation methods of variability and yield
• Fault modeling and simulation
• System-level specification and simulation
• Novel system-level design flows
• Innovative design methodologies enabled by behavioral, performance, and/or symbolic modeling techniques
• Synthesis methods in multi-domain (MEMs, electro-optical, etc.) systems
• Physical synthesis
• High-frequency modeling, simulation and design
• Low-power design techniques
• Parasitic-aware synthesis
• Variability-aware and reliability-aware design methodologies
• Test and design-for-test methods
• Language-based synthesis techniques
• Optimization methods applied to circuit and system design: high-level synthesis, structural synthesis, sizing, etc.
Feb 14, 2012
IM3OLED project to develop multi-scale OLED modelling tool
The EU-funded IM3OLED (Integrated Multidisciplinary & Multiscale Modeling for Organic Light-Emitting Diodes) project has officially been launched.
IM3OLED aims to help the OLED industry speed up development by creating new modelling software that allows a more systematic R&D process. This software toolset will predictively model OLEDs in 3D and at all length scales – from molecular to large-area devices. It will include molecular calculations, electrical and optical simulation, 1D-3D light extraction and scaling / integration effects.
An important aspect of software will be the inclusion of dynamic feedback loops, enabling developers to accurately predict how changes in one area of OLED development affect other areas. This will allow multiple OLED properties to be optimised simultaneously.
The overall device efficiency of an OLED depends on many factors:
This makes it extremely difficult to predict how innovations in one area will affect performance in others, leading to a trial-and-error approach in R&D.
Stephan Harkema, project coordinator, said, “IM3OLED will develop, evaluate and validate a predictive multi-scale and multi-disciplinary modeling tool. Making such a tool available will accelerate progress of OLEDs for lighting applications and allow the European OLED industry to strengthen its leading position in this environmentally important, global market.”
IM3OLED brings together industrial and academic partners from across Europe and the Russian Federation and is coordinated by TNO/Holst Centre and by National Research Nuclear University MEPhI.
Industrial partners include OLED manufacturer Philips Electronics and specialist in simulation software SMEs Fluxim of Switzerland and Kintech of Russia.
Academic partners include leading computational physics and atomic / molecular modelling groups from the Zurich University of Applied Science (ZHAW) and Russian Academy of Sciences’ Photochemistry Center (PCC RAS).
Funded through the European Union’s Seventh Framework Programme (FP7NMP Grant no 295368), the EU portion of the IM3OLED project will run for 30 months until late 2013.
www.im3oled.eu www.holstcentre.com www.mephi.ru
An important aspect of software will be the inclusion of dynamic feedback loops, enabling developers to accurately predict how changes in one area of OLED development affect other areas. This will allow multiple OLED properties to be optimised simultaneously.
The overall device efficiency of an OLED depends on many factors:
- the properties of the light emitting molecules
- deposition on to the substrate
- integration into a device
- extracting the light from the active layer and the device
- heat management and more
This makes it extremely difficult to predict how innovations in one area will affect performance in others, leading to a trial-and-error approach in R&D.
IM3OLED brings together industrial and academic partners from across Europe and the Russian Federation and is coordinated by TNO/Holst Centre and by National Research Nuclear University MEPhI.
Industrial partners include OLED manufacturer Philips Electronics and specialist in simulation software SMEs Fluxim of Switzerland and Kintech of Russia.
Academic partners include leading computational physics and atomic / molecular modelling groups from the Zurich University of Applied Science (ZHAW) and Russian Academy of Sciences’ Photochemistry Center (PCC RAS).
Funded through the European Union’s Seventh Framework Programme (FP7NMP Grant no 295368), the EU portion of the IM3OLED project will run for 30 months until late 2013.
www.im3oled.eu www.holstcentre.com www.mephi.ru
Feb 8, 2012
[mos-ak] MOS-AK/GSA calendar 2012
The MOS-AK/GSA Compact Modeling Committee
have scheduled following four workshops in 2012
<http://www.gsaglobal.org/events/calendar.asp>.
Please mark your calendars and make plans to join us:
have scheduled following four workshops in 2012
<http://www.gsaglobal.org/events/calendar.asp>.
Please mark your calendars and make plans to join us:
*Q1* MOS-AK/GSA Modeling Workshop
http://www.mos-ak.org/india/
DATE: March 16-18, 2012
LOCATION: Noida (U.P.), India
*Q2* MOS-AK/GSA Modeling Workshop
http://www.mos-ak.org/dresden/
DATE: April 26-27, 2012
LOCATION: Dresden, Germany
*Q3* MOS-AK/GSA Modeling Workshop
http://mos-ak.org/bordeaux/
DATE: Sept.21, 2012
LOCATION: Bordeaux, France
*Q4* MOS-AK/GSA Modeling Workshop
http://www.mos-ak.org/
DATE: Dec'2012
LOCATION: San Francisco, CA
Extended MOS-AK/GSA Compact Modeling Committee
http://mos-ak.org/committee.html
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IEEE EDS Webinar: Physics and Technology of Advanced Solar Cells
This email is being sent on behalf of Paul Yu, EDS President,
and Meyya Meyyappan, EDS Vice President of Educational Activities.
Dear Colleague,
As part of our commitment to enhancing the value of membership in EDS, and to advancing the society's mission of fostering the professional growth of its members, we are pleased to invite you to attend a very special Webinar entitled Physics and Technology of Advanced Solar Cells presented by EDS Distinguished Lecturer and IEEE Fellow Prof. Vikram Dalal of Iowa State University. More info available at http://www.mrc.iastate.edu/NewStaff/VikramDalal.htm.
The webinar will take place on Tuesday, February 14 at 3:00 PM Eastern Time (USA). Register for this event
This event is the follow-up to Prof. Dalal's successful talk entitled Introduction to Physics and Technology of Solar Cells which we presented in December.
Watch Replay.
(Note, you will need your IEEE web account login to register and access the video replay)
Title: Physics and Technology of Advanced Solar Cells
Abstract: The Shockley-Queisser (SQ) limit establishes an upper bound to the conversion efficiency of a single junction solar cell. In this talk, the various approaches to overcome the SQ limit will be discussed. Multiple junction solar cells, multi-exciton solar cells, intermediate gap solar cells, and photon up and down conversion to increase efficiency beyond the SQ limit will also be addressed. Multi-junction approaches have succeeded in producing highly efficient III-V solar cells.
In addition, Prof. Dalal will discuss thin film solar cells. These cells, which use polycrystalline, amorphous or organic materials with inferior electronic properties, are now beginning to be widely used for both large scale utility power and for building-integrated and isolated products. Prof. Dalal will address the special physical considerations needed to make efficient solar cells out of these materials, including new schemes for enhancing optical absorption and discuss the status of various technologies.
Attendance will be limited to 500 attendees, offered on a first come, first served basis. As this event is being offered exclusively
to EDS members we request that you do not forward this invitation. Also, given the overwhelming response to our previous webinar,
it would help if you could team up with other EDS members at your institution and thus save a log in port.
Sincerely,
Paul Yu,
EDS President
Meyya Meyyappan,
EDS Vice President of Educational Activities.
Feb 7, 2012
New SPICE Model for Silicon Carbide Power MOSFET
Cree Releases SPICE Model for Silicon Carbide Power MOSFET
Behavior-based model enables power electronic design engineers to quantify benefits of silicon carbide MOSFETs in board-level circuit simulation
See the original press release, or read it here:
DURHAM, N.C., February 6, 2012 — Cree, Inc. (Nasdaq: CREE), a market leader in silicon carbide (SiC) power devices, has expanded its design-in support for the industry’s first commercially-available SiC MOSFET power devices with a fully-qualified SPICE model. Using the new SPICE model, circuit designers can easily evaluate the benefits Cree’s SiC Z-FET™ MOSFETs provide for achieving a higher level of efficiency than is possible with conventional silicon power switching devices for comparably-rated devices.
SiC MOSFETs have significantly different characteristics than silicon devices and therefore require a SiC-specific model for accurate circuit simulations. Cree’s behavior-based, temperature-dependent SPICE model is compatible with the LT spice simulation program and enables power electronics design engineers to reliably simulate the advanced switching performance of Cree CMF10120D and CMF20120D Z-FETs in board-level circuit designs.
Cree SiC MOSFETs are capable of delivering switching frequencies that are up to 10 times higher than IGBT-based solutions. Their higher switching frequencies can enable smaller magnetic and capacitive elements, thereby shrinking the overall size, weight and cost of power electronics systems.
This SiC MOSFET SPICE model adds to Cree’s comprehensive suite of design-in support tools, technical documentation, and reliability information to provide power electronics engineers with the design resources necessary to implement SiC power devices into the next generation of power systems.
The Cree SiC MOSFET SPICE model is available for download at www.cree.com/power/mosfet.asp. In addition, customers can download published specifications and detailed design guidelines and request samples. For more information about Cree’s SiC power devices, please visit www.cree.com/power.
About Cree
Cree is a market-leading innovator of semiconductor products for power and radio-frequency (RF) applications, lighting-class LEDs, and LED lighting solutions.
Cree's product families include LED fixtures and bulbs, blue and green LED chips, high-brightness LEDs, lighting-class power LEDs, power-switching devices and RF devices. Cree products are driving improvements in applications such as general illumination, electronic signs and signals, power supplies and solar inverters.
For additional product and company information, please refer to www.cree.com
This press release contains forward-looking statements involving risks and uncertainties, both known and unknown, that may cause actual results to differ materially from those indicated. Actual results may differ materially due to a number of factors, including customer acceptance of our products; the rapid development of new technology and competing products that may impair demand or render Cree’s products obsolete; and other factors discussed in Cree’s filings with the Securities and Exchange Commission, including its report on Form 10-K for the year ended June 26, 2011, and subsequent filings.
Cree is a trademark registered in the U.S. Patent and Trademark Office by and Z-FET is a trademark of Cree, Inc.
Media Contact:
Michelle Murray
Cree, Inc.
Corporate Communications
(919) 313-5505
michelle_murray@cree.com
Behavior-based model enables power electronic design engineers to quantify benefits of silicon carbide MOSFETs in board-level circuit simulation
See the original press release, or read it here:
DURHAM, N.C., February 6, 2012 — Cree, Inc. (Nasdaq: CREE), a market leader in silicon carbide (SiC) power devices, has expanded its design-in support for the industry’s first commercially-available SiC MOSFET power devices with a fully-qualified SPICE model. Using the new SPICE model, circuit designers can easily evaluate the benefits Cree’s SiC Z-FET™ MOSFETs provide for achieving a higher level of efficiency than is possible with conventional silicon power switching devices for comparably-rated devices.
SiC MOSFETs have significantly different characteristics than silicon devices and therefore require a SiC-specific model for accurate circuit simulations. Cree’s behavior-based, temperature-dependent SPICE model is compatible with the LT spice simulation program and enables power electronics design engineers to reliably simulate the advanced switching performance of Cree CMF10120D and CMF20120D Z-FETs in board-level circuit designs.
Cree SiC MOSFETs are capable of delivering switching frequencies that are up to 10 times higher than IGBT-based solutions. Their higher switching frequencies can enable smaller magnetic and capacitive elements, thereby shrinking the overall size, weight and cost of power electronics systems.
This SiC MOSFET SPICE model adds to Cree’s comprehensive suite of design-in support tools, technical documentation, and reliability information to provide power electronics engineers with the design resources necessary to implement SiC power devices into the next generation of power systems.
The Cree SiC MOSFET SPICE model is available for download at www.cree.com/power/mosfet.asp. In addition, customers can download published specifications and detailed design guidelines and request samples. For more information about Cree’s SiC power devices, please visit www.cree.com/power.
About Cree
Cree is a market-leading innovator of semiconductor products for power and radio-frequency (RF) applications, lighting-class LEDs, and LED lighting solutions.
Cree's product families include LED fixtures and bulbs, blue and green LED chips, high-brightness LEDs, lighting-class power LEDs, power-switching devices and RF devices. Cree products are driving improvements in applications such as general illumination, electronic signs and signals, power supplies and solar inverters.
For additional product and company information, please refer to www.cree.com
This press release contains forward-looking statements involving risks and uncertainties, both known and unknown, that may cause actual results to differ materially from those indicated. Actual results may differ materially due to a number of factors, including customer acceptance of our products; the rapid development of new technology and competing products that may impair demand or render Cree’s products obsolete; and other factors discussed in Cree’s filings with the Securities and Exchange Commission, including its report on Form 10-K for the year ended June 26, 2011, and subsequent filings.
Cree is a trademark registered in the U.S. Patent and Trademark Office by and Z-FET is a trademark of Cree, Inc.
Media Contact:
Michelle Murray
Cree, Inc.
Corporate Communications
(919) 313-5505
michelle_murray@cree.com
Feb 6, 2012
SISPAD 2012, Denver, CO, USA, Call for Papers
|
| ||
| Call for Papers
Date and Location
The abstract should describe the nature of the presentation, together with references. The text must be single-spaced with 11pt or 12pt font. The abstract is limited to two pages including figures, tables and references. Abstracts should be submitted in PDF format. For more information, please visit: |
Jan 27, 2012
Execs gather at SEMI ISS
From Semiconductor Manufacturing and Design:
At SEMI's Industry Strategy Symposium (ISS), Applied Materials CEO Mike Splinter urged creation of a forum for equipment makers to provide input to the Global 450 Consortium (G450C). Splinter said collaboration is needed to tackle the 450mm transition, which could have an R&D t tag of $15-20 billion.
Speaking at ISS, an ASML executive put some hard numbers on the expected performance of the forthcoming commercial EUV tool. The NXE:3300 EUV scanners will start out with throughput rated at 69 wafers an hour, said James Koonmen.
The chip industry's three biggest spenders are bullish. Intel said it will up its capex spending for 2012, with more than a third of the $12.5 billion going into 14nm fab construction in Oregon and Arizona. Intel also promoted a manufacturing executive, Brian Krzanich, to chief operating officer, as part of a wider reorganization.
TSMC chairman Morris Chang said much of the foundry's $7 billion in 2012 capex is going into building new fabs in Taichung and Hsinchu, in preparation for 20nm risk production late next year. Samsung also is spending heavily, with capital expenditures of $29 billion going into making semiconductors and displays for mobile systems. More than a billion dollars is expected to go toward expanding logic IC capacity at its Austin fab.
KLA-Tencor said it has done a grounds-up redesign of its 2900 broadband wafer inspection tool, and upgraded its narrowband and e-beam wafer inspection systems as well.
SemiMD senior editor Mark LaPedus reported "there are more rumors that Micron Technology Inc. will make a bid for debt-ridden Elpida Memory Inc."
At SEMI's Industry Strategy Symposium (ISS), Applied Materials CEO Mike Splinter urged creation of a forum for equipment makers to provide input to the Global 450 Consortium (G450C). Splinter said collaboration is needed to tackle the 450mm transition, which could have an R&D t tag of $15-20 billion.
Speaking at ISS, an ASML executive put some hard numbers on the expected performance of the forthcoming commercial EUV tool. The NXE:3300 EUV scanners will start out with throughput rated at 69 wafers an hour, said James Koonmen.
The chip industry's three biggest spenders are bullish. Intel said it will up its capex spending for 2012, with more than a third of the $12.5 billion going into 14nm fab construction in Oregon and Arizona. Intel also promoted a manufacturing executive, Brian Krzanich, to chief operating officer, as part of a wider reorganization.
TSMC chairman Morris Chang said much of the foundry's $7 billion in 2012 capex is going into building new fabs in Taichung and Hsinchu, in preparation for 20nm risk production late next year. Samsung also is spending heavily, with capital expenditures of $29 billion going into making semiconductors and displays for mobile systems. More than a billion dollars is expected to go toward expanding logic IC capacity at its Austin fab.
KLA-Tencor said it has done a grounds-up redesign of its 2900 broadband wafer inspection tool, and upgraded its narrowband and e-beam wafer inspection systems as well.
SemiMD senior editor Mark LaPedus reported "there are more rumors that Micron Technology Inc. will make a bid for debt-ridden Elpida Memory Inc."
Jan 20, 2012
[mos-ak] C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18, 2012
C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18,
2012
2012
Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
JIIT, Noida (U.P.) India, March 16-18, 2012 with the tutorial on CMOS
technology and SPICE Models by Dr. N.D. Arora, Silterra, Malaysia.
List of the international modeling experts contributing to the MOS-AK/
GSA Workshop includes following names (in alphabetic order)
* Nanrian D. Arora, Silterra, Malaysia
* Navakanta Bhat, IISC Bangalore, India
* A.B. Bhattacharyya, JIIT Noida, India
* Mike Brinson, London Metropolitan University, UK
* Amitava Dasgupta, IIT Chennai, India
* Christian Enz, EPFL, Switzerland
* Tamilmani Ethirajan, IBM, India
* Thomas Gneiting, ADMOS, Germany
* Wladek Grabinski, MOS-AK/GSA
* Andre Juge, STM, France
* M. Jagdesh Kumar, IIT Delhi, India
* Shantanu Mahapatra, IISc, India
* Mitiko Miura-Mattausch, Hiroshima University, Japan
* Ramgopal Rao, IIT Mumbai
* Samar Saha, IEEE
* Manoj Saxena, University of Delhi, India
* Ehrenfried Seebacher, AMS, Austria
* Vaidyanathan Subramanian, IBM, India
* Xing Zhou, NTU, Singapore
The terms of participation:
* To register please visit the INAE website <http://inae.org/
seminar.htm> and complete the registration form
* Poster abstract submission with the deadline on Jan. 31, 2012.
Posters' abstract of maximum 300 words and paper of maximum 5 pages in
A4 size double spaced two columns should be submitted to Prof. AB
Bhattacharyya at <inaehq@gmail.com>
Intending participants and authors should also note the following
deadlines:
* Announcement and Call for Papers - Q4 2012
* Poster abstract submission deadline - Jan.31, 2012
* Final Workshop Program - Feb. 2012
* MOS-AK/GSA Workshop - March 16-18, 2012
Further details and updates: <http://www.mos-ak.org/india>
Email contact: <india@mos-ak.org>
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Jan 11, 2012
[mos-ak] MOS-AK/GSA Washington DC on-line publications
MOS-AK/GSA Washington DC workshop on-line publications are available,
visit:
http://mos-ak.org/washington_dc/
visit:
http://mos-ak.org/washington_dc/
I would like to thank all MOS-AK/GSA speakers for sharing their
compact modeling competence, R&D experience and delivering valuable
MOS-AK/GSA presentations. I am sure, that our modeling event in
Washington DC was a beneficial on to all the attendees as well as to
all MOS-AK/GSA Group.
I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).
- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––----------------
http://mos-ak.org/committee.html
––––––––––––––––––––––––––––––––––----------------
MOS-AK/GSA India March 16-17, 2012
<http://mos-ak.org/india/>
MOS-AK/GSA Dresden April 26-27, 2012
<http://mos-ak.org/dresden/>
MIXDES Special Modeling Sesion Warsaw May 24-26, 2012
<https://www.mixdes.org/Special_sessions.htm>
MOS-AK/GSA Bordeaux Sept.21, 2012
<http://goo.gl/bUrsp>
MOS-AK/GSA San Francisco Q4 2012
––––––––––––––––––––––––––––––––––----------------
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EPFL Post-doctoral/ experienced engineer position
Candidate will integrate the Swiss CTI project CAPED for a period of 18 months. This research project aims at
developing new technologies based on low power wireless communications, for communication between one
intelligent pill implanted in the digestive system and an external control unit. The main industrial partner of
this project is the Swiss company Motilis Medica SA. Dr. Catherine Dehollain
(RF IC group leader) is the scientific coordinator of this project.
We are looking for one post-doc/ experienced engineer specialized in low power microelectronic integrated
circuits with strong practical experience in the following topics:- Design of CMOS low power integrated circuits (analog, mixed-mode and RF blocks)
- Design of CMOS low power integrated circuits for energy scavenging (AC to DC converter, voltage regulator, bandgap reference circuit, power-on-reset circuit, etc)
- Design of CMOS power management circuits
- Design of CMOS low power transmitter and receiver (LNA, PLL, VCO, mixer, filters, etc) for wireless communications
- Practical experience in the measurements of CMOS integrated circuits EDA tools dedicated to the design of integrated circuits (e.g. Cadence, Agilent ADS, Pspice, etc)
The RF IC group provides a stimulating environment, good working conditions, and collaborations within a team of 10 researchers and PhD students working on related projects.
- Starting date: as soon as possible.
- Contract duration: 18 months
Application has to include a CV, copies of the diplomas, significant published or unpublished papers, motivation letter and three letters of reference (or submit 3 reference names). Please send your application at the latest at the end of February 2012 to Dr. Catherine Dehollain
Jan 9, 2012
C4P: 2012 IEEE Silicon Nanoelectronics Workshop
Hilton Hawaiian Village in Honolulu, Hawaii (June 10-11, 2012)
Sponsored by the IEEE Electron Device Society
Scope:
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]
Sponsored by the IEEE Electron Device Society
Authors are encouraged to submit a full-length paper to the IEEE Transactions on Nanotechnology or the IEEE Transactions on Electron Devices.
Download the Call for Papers (PDF format)
Further Information
The 2012 Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It will be held on June 10-11, 2012 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the seventeenth workshop in the annual series. Original papers on nanometer-scale devices and technologies which utilize silicon or which are based on silicon substrates are welcome.
Prospective authors are requested to submit an abstract in PDF format, consisting of one page of text and one page of figures. It must include the paper title, the authors’ names and affiliation(s), and the full contact information (mailing address, phone and FAX numbers, e-mail address) for the corresponding author. Accepted abstracts will be reproduced in the workshop proceedings exactly as received. Some of the accepted papers will be presented in Poster Sessions. The deadline for receipt of abstracts is 5PM (Pacific Time) April 1, 2012. Authors will be notified by April 30, 2012.
Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2012 VLSI Technology Symposium (http://www.vlsisymposium.org/index.html).Scope:
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]
Jan 3, 2012
Price per transistor on a chip
The price per transistor on a chip has dropped dramatically since Intel was founded in 1968. Some people estimate that the price of a transistor is now about the same as that of one printed newspaper character.
Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]
Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]
25th ICMTS Conference
SAN DIEGO March 19-22, 2012
| Day 1 | Day 2 | Day 3 |
|---|---|---|
| 08:45 Registration | 09:00 Registration | 09:00 Registration |
| 08:45 Welcome | 09:00 Process Characterization | 09:00 Matching |
| 08:55 Design Margin | 11:10 RF | 10:50 Capacitance |
| 10:45 Variability | 12:10 ICMTS 2013 | 12:10 Closing |
| 11:45 Exhibitor Presentation | 13:50 Parameter Extraction | |
| 13:45 MEMS | 16:00 Stress | |
| 15:55 Poster |
Note: This program is subject to change without notice. Final printed version of program will be available at the conference.
Scientific employee, PhD student, or postdoc at TU Dresden
in circuit design
on organic, flexible, roll-to-roll-printed & plastic-based semiconductor technologies
The period of employment is governed by the Fixed Term Research Contracts Act (Wissenschaftszeitvertragsgesetz - WissZeitVG). The position is in the frame of the FLEXIBILITY (Flexible Multifunctional Bendable Integrated Light-Weight Ultra-Thin Systems) project funded by the EU involving 7 industry partners and 4 research institutions. PhD students will find excellence prerequisites for an innovative PhD thesis. The first wireless communication receiver fully integrated in a piece of plastic foil (without the need for a silicon chip) will be developed. The project is coordinated by our chair and provides an excellent platform for interdisciplinary cooperation with industry partners.
Tasks:
Design (analyses, simulation, device modelling, layout, testing and documen-tation) of circuits and systems operating up to radio frequencies in novel OLAE (Organic and Large Area Electronics) and roll-to-toll printed technologies for wireless communications. The authoring of scientific publications and the participation at project meetings and international conferences are expected. The active involvement in project management is planned for postdocs.
Requirements:Excellent to good master, Dipl.-Ing. or PhD degree in microelectron-ics, electrical engineering, physics or chemistry. Knowledge in circuit design, inde-pendent and flexible working attitude, innovative and analytical thinking, strong commitment, communicative team-player, good English. Knowledge in the following areas is advantageous: Integrated circuit design, OLAE, device modelling, high frequency engineering, communications and semiconductor technologies, measure-ment techniques, German language.
Miscellaneous:
Applications from women are particularly welcome. The same applies to the disabled. Interested candidates are requested to submit concise application material including CV and copy of certificates per email in pdf format to Frank.Ellinger@tu-dresden.de [read more...]
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