Lynguent Debuts Radiation Hardened By Design, BSIM4 Compact Model Toolkits

Lynguent®, Inc., announced two new toolkits for its ModLyng[tm] Integrated Modeling Environment (IME): Radiation Hardened By Design (RHBD) Toolkit and BSIM4 Compact Model Toolkit. The RHBD Toolkit includes models and tools which provide a modeling and analysis capability for Single Event Upset (SEU) behaviors in deep sub-micro processes. The BSIM4 Compact Model Toolkit includes a high fidelity BSIM4 model which provides more flexibility than has ever been available for adding new effects to existing processes built upon the BSIM foundation. These toolkits, when used with the ModLyng IME, enable semiconductor and systems companies to easily enhance their IC design flows with radiation SEU capability and thus save weeks in qualifying their designs and cell libraries for radiation hardness.

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New Book:

Compact MOSFET Models for VLSI Design
A. B. Bhattacharyya
ISBN: 978-0-470-82342-2
Hardcover 512 pages April 2009


This book is essential for students specializing in VLSI Design and indispensible for design professionals in the microelectronics and VLSI industries. Written to serve a number of experience levels, it can be used either as a course textbook or practitioner’s reference. Read more...

Access the MATLAB code, solution manual, and lecture materials at the companion website.

IC Insights expects an 18% "surge" in the IC market

I post here a very interesting article, even if not related to compact modelling, from EDN:(visit them for more interesting articles)

IC market second-half 'surge' predicted

IC Insights expects an 18% "surge" in the IC market in the second half of the year and claims there is clear evidence that the much-anticipated turning point toward recovery has already occurred.

By Suzanne Deffree, Managing Editor, News -- Electronic News, 7/2/2009

The second half of 2009 will be much better than the first for the semiconductor industry, and will be marked by an IC market "surge," according to IC Insights.

The market research company this week reported that while the first half of 2009 was hit hard by seasonal weakness for electronic system sales, a major IC inventory adjustment, and the global recession at its worst, the second half of 2009 is expected to usher in strong seasonal strength for electronic system sales, a period of IC inventory replenishment, and positive worldwide GDP growth.

"In IC Insights' opinion, the bottom of the current cycle in the worldwide economy and semiconductor industry was reached in Q1 2009," Bill McClean, president of IC Insights, said in a statement on the company's mid-year update. "While the 'velocity' of the semiconductor industry recovery is subject to debate (slow, moderate, fast, etc), at least the discussion over the next few quarters will be about how much sequential growth can be expected in instead of how far the markets are going to fall."

Also see: Demand surge expected in second half, IC Insights says Major upsets in semiconductor top 20 ranking, IC Insights reports Bottom hit in Q1, 5% growth for Q2 expected, IC Insights reports

IC Insights has long been encouraging the idea that, when viewed on a quarterly basis, a much more positive and "relevant" outlook business conditions can be achieved.

For example, according to the company's data, worldwide GDP growth is forecast to be negative this year of down 0.8% on a weak first half with growth down, but the second half of the year is expected to register positive growth of 2%. (See figure 1 below.) The same pattern is forecast for the US economy, as well, with the second half showing growth of 1.3% as compared to the first half.

Specific to the electronics industry, IC Insights reported seasonal strength is likely to propel second-half cell phone and PC unit shipments up by 18% and 15%, respectively, as compared to the first half.

Overall, IC Insights said it expects an 18% "surge" in IC market sales in the second half, as compared to the first half. "In fact, the double-digit Q2 2009/Q1 2009 IC market increase is clear evidence of the fact that the much-anticipated turning point has already occurred," McClean said.

According to IC Insights, the IC foundry market is expected to continue its "sharp recovery" in the second half of 2009. McClean noted that the IC foundry market almost doubled in Q2 as compared to Q1.

"There is no doubt that, as a group, the semiconductor equipment suppliers have taken the worst 'beating' of any of the companies involved in the current semiconductor industry downturn," McClean said. "However, the second half of 2009 is expected to offer some relief for these suppliers as semiconductor industry capital spending is forecast to jump by 28% as compared to the first half of 2009."

McClean noted that many of the major semiconductor suppliers that IC Insights tracks are planning to spend the majority of their capital spending budgets in the second half of 2009. Offering example, he said Hynix spent 30% of its 2009 spending budget in the first half, but plans to spend the remaining 70% in the second half.

Old glories never die... do they?

It's quite hard for an old glory like HSPICE to die. See the post in aboutSpice.com:
SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development (Synopsys)

Have a nice summertim

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An Insider’s View to the Swiss LP/LV CMOS Design History

Organizers: Jean-Michel Sallese; EPFL and Wladek Grabinski; GMC Consulting
Host: Predrag Habas; EM Marin

Where: EPFL - Swiss Federal Institute of Technology, Lausanne, Room CO017
When: Friday, July 3, 2009, 5:00 pm

Title: An Insider’s View to the Swiss LP/LV CMOS Design History
Presenter: Stefan Cserveny

Abstract: I worked the last 30 years at CEH - CSEM, the amazing Swiss crucible at the origin of the very low power integrated circuits, taking advantage of its highly professional, creative and enthusiastic teams and the close and fruitful collaboration with the EPFL and the Swiss industry. I will present some of these historical developments as viewed by the subjects in which I had the opportunity to add my contribution. After a short overview of my background and work done before joining the CEH, I will first present the early compact MOS modeling work done in order to satisfy the requirements for the LP/LV design including the near threshold range - a work setting the path towards the presently largely used EKV model. The following items are some of the sensor interface circuits, the realization of embedded low power non-volatile memories and, finally, the very low leakage SRAM memories essential for many critical applications.

Short Bio: Stefan Cserveny is retiring after 47 years of teaching and research and development activities as an electron device engineer and as a circuit designer, especially for designs requiring device expertise. The first 17 years he lectured electron devices and circuits at the Polytechnic Institute of Bucharest, Romania and at the Telecommunication Institute of Oran, Algeria, which he helped to create, writing several textbooks and scientific papers. In 1972 he obtained a one year specialization grant he spent at the University of California Berkeley where he received the M.S. degree in electrical engineering. In 1979 he joined the 17 years old CEH, which in 1984 became part of CSEM, getting involved with the LP/LV challenge first needed for the watch industry. In his position of scientific expert he contributed to research projects and ASIC developments; most interesting results have been published. He also participated in the BCTM technical program committee, reviewed a large number of papers and did consulting for Swiss companies.

QUCS developments

The QUCS development team is taking part in the MOS Modelling and Extraction Working Group (MOS-AK) Verilog-A standardisation initiative.

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The QUCS Team is also contributing to the MIXDES special session "Device Level Support for Emerging CMOS Technologies" organised by Daniel Tomaszewski; ITE, Poland and Wladek Grabiński; GMC Suisse (with MOS-AK/GSA Group and COMON EU Project coordination)

Read the QUCS paper's abstract: "Compact Device Modeling for Established and Emerging Technologies with the Qucs GPL Circuit Simulator"

Future Solutions of System On Chip (SoC)

Frédéric Boeuf, Principal Engineer at STM, gave a short course at the VLSI Symposium 2009 in Kyoto. It is a synthesis on the silicon technology uses for system on chip applications, and some prospect about the future solutions.

View the slide presentation...