Here I am, back to real world after two weeks of conferences. I must confess that I'm happy to be at home again. Well, to the point. The last one of the conferences was a bit disappointing, because it was mainly dedicated to solar cells in the oral sessions. This is so because it was organized by the Solar Energy Institute. The poster sessions were more interesting, with many different topics, though the only ones dedicated to compact modeling were some posters from B. Iñiguez and Toni Lazaro, dedicated mainly to double gate and RF modeling. Quite interesting, even if they didn't win the best paper award (by the way, only five of the six awards went to people related to the organizers).
Another poster I was happy to see was one about pi-gate FETs, where they were modeling the transistor using some device simulator. The funny thing was to see the double threshold effect, with some explanantions about it.
Feb 5, 2007
Jan 31, 2007
IET (former IEE) Award
Today I've learnt that the Institution of Engineering and Technology has awarded the Circuits, Devices and Systems Premium, to B. Iniguez, J. Deen and O. Marinov, for the paper “Charge Transport in Organic and Polymer Thin-Film Transistors: Recent Issues”.
Congratulations!
Congratulations!
Jan 30, 2007
CDE in Madrid
Today I'm leaving for the CDE in Madrid. It is a Spanish conference, though with many international attendants. This year it is mainly focused on photonics, but there are many papers (and posters) on compact modeling. I'll report on this conference next week, with some comments on the best (under my own criteria) papers.
Jan 29, 2007
About the ITC'07 in Rome
Well, it has been a little bit disappointing, because though there were near 100 works, only four of them were on compact modeling. However, the rest of all has been very interesting, and I've learn more than I ever wanted to know about fabrication processes...
Once everything is added up, I'd like to point out some papers: one of Plastic Logic, Ltd where they were presenting statistics about defects in their fabricated circuits (panels), and another from Canon and the Tokyo Institute of Technology.
The latter was about parameter dispersion on TFT, one thing I believe to be quite forgotten about in compact modeling and very (VERY) important for design. The paper is good, but it lets out many things (effects of separation, orientation, mismatch in size, correlations among variations, etc...) However, it is a good start.
Once everything is added up, I'd like to point out some papers: one of Plastic Logic, Ltd where they were presenting statistics about defects in their fabricated circuits (panels), and another from Canon and the Tokyo Institute of Technology.
The latter was about parameter dispersion on TFT, one thing I believe to be quite forgotten about in compact modeling and very (VERY) important for design. The paper is good, but it lets out many things (effects of separation, orientation, mismatch in size, correlations among variations, etc...) However, it is a good start.
Jan 23, 2007
The European Network of Excellence "SINANO" addressed Compact Modelling of Multiple-Gate MOSFETs
From January 2004 to December 2006, a number of European teams have been working together in a Network of Excellence called SINANO, devoted to the study of novel structures of Silicon nanodevices.
The work has included technology, characterization, advanced simulation and compact modeling of novel structures of nanoscale MOSFETs.
The compact modeling work has especially addressed Multuple-Gate MOSFETs, in particular Double-Gate (DG) and Gate All Around (GAA) MOSFETs. The joint effort on compact modeling has led to several publications in international journals and conference proceedings.
Among the compact modeling publications carried out under the umbrella of the SINANO Network of Excellence, I want to mention the following paper, which was invited to the Special Issue on Advanced Compact Models and 45-nm Modeling Challenges, of IEEE Transactions on Electron Devices:
B. Iñiguez, T. A., Fjeldly, A. Lazaro, F. Danneville and M. J. Deen, “Compact-modeling solutions for nanoscale double-gate and gate-all-around MOSFETs,” IEEE Trans. on Electron Devices, vol 53, no. 9, pp. 2128-2142 September 2006
The work has included technology, characterization, advanced simulation and compact modeling of novel structures of nanoscale MOSFETs.
The compact modeling work has especially addressed Multuple-Gate MOSFETs, in particular Double-Gate (DG) and Gate All Around (GAA) MOSFETs. The joint effort on compact modeling has led to several publications in international journals and conference proceedings.
Among the compact modeling publications carried out under the umbrella of the SINANO Network of Excellence, I want to mention the following paper, which was invited to the Special Issue on Advanced Compact Models and 45-nm Modeling Challenges, of IEEE Transactions on Electron Devices:
B. Iñiguez, T. A., Fjeldly, A. Lazaro, F. Danneville and M. J. Deen, “Compact-modeling solutions for nanoscale double-gate and gate-all-around MOSFETs,” IEEE Trans. on Electron Devices, vol 53, no. 9, pp. 2128-2142 September 2006
(This is an excellent review of the compact modeling work carried so far in Multiple-Gate devices and provides very interesting solutions for a 2-D or 3-D analytical model)
ITC in Rome
Well, today I'm leaving for the International Thin-Film Transistor in Rome, so the blog is going to be un-updated until I come back. However, I promise a (quite) full report when I return.
Jan 22, 2007
A historical note
This post is a historical hint. This weekend I've been surfing the internet, and I've been looking for some pages on Spice history. Why Spice? Well, all of you know that if spice (or similar) didn't exist, then probably the semiconductor revolution wouldn't have taken place. The first link is to the wikipedia, where they put a quite extensive article about it, including even a list of commercial and free simulators. Only a little comment: In the list they include Eldo, and I think that I should note that, while Eldo is in fact a simulator, it is one of the few that is not Spice-based. Another link is to the page of ecircuitcenter, where they put quite the same information, but in the format of list, which is maybe clearer.
The basic facts about the name "Spice" are few: created as a class project by Larry Nagel (under supervision of Ron Rohrer) it was first called CANCER (Computer Analysis of Non-Linear Circuits Excluding Radiation), because of the time it was created. In 1972 (yes, that's before I was born...), the final name SPICE (Simulation Program with IC Emphasis) was introduced. And that's all about the name. Another day, I'll talk about other features of this simulator.
The basic facts about the name "Spice" are few: created as a class project by Larry Nagel (under supervision of Ron Rohrer) it was first called CANCER (Computer Analysis of Non-Linear Circuits Excluding Radiation), because of the time it was created. In 1972 (yes, that's before I was born...), the final name SPICE (Simulation Program with IC Emphasis) was introduced. And that's all about the name. Another day, I'll talk about other features of this simulator.
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