[paper] Future of Ultra-Low Power SOTB CMOS

Nobuyuki Sugii¹, Shiro Kamohara², Makoto Ikeda³

The Future of Ultra-Low Power SOTB CMOS Technology and Applications

NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham

DOI: 10.1007/978-3-030-18338-7_6

1.Hitachi, Ltd.Tokyo, Japan
2.Renesas Electronics Corp.Tokyo, Japan
3.The University of Tokyo, Japan

Abstract: Ultra-low power technology has drawn much attention recently as the number of connecting (Internet-of-Things) devices rapidly increases. The silicon-on-thin-buried oxide (SOTB) technology is a CMOS device technology that uses fully depleted silicon-on-insulator (FDSOI) transistors with a thin buried oxide layer enabling enhanced back-bias controllability and that can be monolithically integrated with the conventional bulk CMOS circuits. It can significantly reduce both the operation and the standby powers by taking advantage of low-voltage operation and back-biasing, respectively. In this chapter, advantages of the SOTB technology in terms of ultra-low power, circuits design and chip implementation examples including ultra-low power micro-controllers operating with harvested power, reconfigurable logic circuits, analog circuits, are reviewed, and a future perspective is shown.

Fig.: Schematic cross section of SOTB transistors. Hybrid bulk transistors are shown. SOTB  transistors are used in low-voltage (< ~1.5 V) logic and analog circuits including SRAMs. Bulk  transistors are used in peripheral, ESD-protection, high-voltage analog and power circuits, on-chip,  flash memory, and reuse of legacy circuits

Acknowledgements: The part of the work, especially on developing the SOTB technology by the Low-power Electronics Association and Project (LEAP), is supported by the Ministry of Economy, Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO). Part of the chip fabrication by the universities is done under a support of VLSI Design and Education Center (VDEC) in collaboration with Renesas Electronics Corporation, Cadence Corporation, Synopsys Corporation and Mentor Graphics Corporation.

IEEE PS Webinar "G2V and V2G Technologies in Electric Vehicles"

IEEE Photonics Society Student Chapter of Mangalam College of Engineering is geared up with webinar series to provoke the little spark in you

• Date:16-06-2020
• Time:10:30 - 11:30 AM IST
• Pre registration link: https://bit.ly/3dTeDzP
• Topic: G2V and V2G Technologies in Electric Vehicles
• Speaker: Dr.Sreejith.S; Assistant Professor,
  Department of Electrical Engineering,
  National Institute of Technology, Silchar, Assam

We, IEEE Photonics Society Student Chapter, invite you all to join this webinar and take away some useful stuffs in this quarentine. Registration free!!! See you there. All registered participants are honoured with e-certificates

Webinar Link: https://bit.ly/2ZgJuBY
For further queries contact our coordinators:
Alsufiyan   : +91 7736598136
Nandhu : +91 9061383258

Stay Safe, Enjoy learning!! Stay updated with us for more exciting events!...

[paper] Organic Permeable Base Transistors

Darbandy, G., Dollinger, F., Formánek, P., Hübner, R., Resch, S., Roemer, C., Fischer, A., Leo, K., Kloes, A., Kleemann, H., 

Unraveling Structure and Device Operation of Organic Permeable Base Transistors

Adv. Electron. Mater. 2020, 2000230 

DOI 10.1002/aelm.202000230

Abstract: Organic permeable base transistors (OPBTs) are of great interest for flexible electronic circuits, as they offer very large on‐current density and a record‐high transition frequency. They rely on a vertical device architecture with current transport through native pinholes in a central base electrode. This study investigates the impact of pinhole density and pinhole diameter on the DC device performance in OPBTs based on experimental data and TCAD simulation results. A pinhole density of N Pin = 54 µm−2 and pinhole diameters around L Pin = 15 nm are found in the devices. Simulations show that a variation of pinhole diameter and density around these numbers has only a minor impact on the DC device characteristics. A variation of the pinhole diameter and density by up to 100% lead to a deviation of less than 4% in threshold voltage, on/off current ratio, and subthreshold slope. Hence, the fabrication of OPBTs with reliable device characteristics is possible regardless of statistical deviations in thin film formation.

Fig.: Device stack of an OPBT. The central base electrode is permeable to electrons. The device current flows between emitter and collector, while the base layer is passivated by an oxide layer.

The device current can be modulated by the base‐emitter voltage V_BE

Acknowledgements: G.D. and F.D. contributed equally to this work. This project was funded by the German Research Foundation (DFG) under the grants KL 1042/9‐2 and LE 747/52‐2 (SPP FFlexCom) and by the European Community’s Seventh Framework Programme under Grant Agreement No. FP7‐267995 (NUDEV). This work was supported in part by the German Research Foundation (DFG) within the Cluster of Excellence Center for Advancing Electronics Dresden (cfaed) and the DFG project HEFOS (Grant No. FI 2449/1‐1). Furthermore, the use of HZDR Ion Beam Center TEM facilities and the funding of TEM Talos by the German Federal Ministry of Education of Research (BMBF; grant No. 03SF0451) in the frame‐work of HEMCP are acknowledged. The authors thank Tobias Günther and Andreas Wendel of IAPP for sample preparation.

[paper] GaN/AlGaN 2DEGs grown on bulk GaN

Luisa Krückeberg¹,  Steffen Wirth²,  Victor V. Solovyev³, Andreas Großer¹, Igor V. Kukushkin^3,4,  Thomas Mikolajick^1,5, and  Stefan Schmult⁵

Quantum and transport lifetimes in optically induced GaN/AlGaN 2DEGs

grown on bulk GaN

Journal of Vacuum Science and Technology B 38, 042203 (2020)

DOI: 10.1116/1.5145198

¹NaMLab GmbH, Dresden (D)
²Max-Planck-Institute for Chemical Physics of Solids, Dresden (D)
³Institute of Solid State Physics RAS, Moscow (RU)
⁴National Research University Higher School of Economics, Moscow (RU)
⁵Institute of Semiconductors and Microsystems, TU Dresden, Dresden (D)

ABSTRACT A two-dimensional electron gas (2DEG) is absent in ultrapure GaN/Al0.06Ga0.94N heterostructures grown by molecular beam epitaxy on bulk GaN at 300 K and in the dark. However, such a 2DEG can be generated by UV illumination and persists at low temperature after blanking the light. Under steady UV illumination as well as under persistence conditions, pronounced quantum transport with Shubnikov–de Haas oscillations commencing below 2 T is observed. The low temperature 2DEG mobility amounts to only ∼20 000 cm2/V s, which is much lower than predicted for the dominant scattering mechanisms in GaN/AlGaN heterostructures grown on GaN with low threading dislocation density. A rather small ratio of the transport and quantum lifetimes τt/τq of ∼10 points at elastic scattering events limiting both the transport and quantum lifetimes.

FIG. (a) Photograph of a Hall bar device and (b) its two-terminal resistance R2pt at stabilized temperatures between 120 and 135K. The estimated UV power during illumination is in the low nanowatts range, which does not result in a saturation of R2pt at these specific temperatures. The recombination time, i.e., the time until disappearance of the 2DEG, increases significantly at 120K. At 100 K, no increase in R2pt is observed after switching off the illumination.

ACKNOWLEDGMENTS The NaMLab gGmbH part was financially supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation)—Project No. 405782347, the German Federal Ministry of Education and Research—BMBF (Project “ZweiGaN,” No. 16ES0145K), and the German Federal Ministry of Economics and Technology—BMWi (Project No. 03ET1398B). V.V.S. and I.V.K. acknowledge the support from the Russian Science Foundation (Grant No. 19-42-04119). The TU Dresden part of the work was partially funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation)—Project No. 348524434.

[paper] Nanowire gate-all-around MOSFETs modeling

Cheng, He, Tiefeng Liu, Chao Zhang, Zhijia Yang, Zhifeng Liu, Kazuo Nakazato

and Zhipeng Zhang

Nanowire gate-all-around MOSFETs modeling:

ballistic transport incorporating the source-to-drain tunneling

Japanese Journal of Applied Physics (2020)

Accepted Manuscript online 5 June 2020

DOI: 10.35848/1347-4065/ab99db

Abstract: Incorporating the source-to-drain tunneling current valid in all operating regions, an analytical compact model is proposed for cylindrical ballistic GAA-nMOSFETs with ultra-short Silicon channel. From taking the DIBL effect into consideration, the potential distribution within the device channel has been modeled based upon a 2-D analysis in our previous work. In this study, by introducing a parabolic function when modeling the potential profile in the channel direction, we found out that the source-to-drain tunneling effect in the subthreshold region could be evaluated analytically by applying WKB approximation. Then, it is practical to estimate the drain current for all operating regions analytically with this compact model considering both the source-to-drain tunneling and thermionic transport. The resulting analytic compact model is tested against NEGF simulation using SILVACO, and good accuracy is demonstrated. Finally, we perform an NMOS inverter circuit simulation using HSPICE, introducing our model to it as a Verilog-A script.

Fig: Rough sketch of the potential energy profile along the channel and illustration of mechanisms governing the carrier transport in ballistic tunneling and thermionic modes.
(a) Representation of energy levels distribution along the z-direction at the channel center (r = 0).
(b) Schematics of confinement potential energy distribution along r-component at the barrier top (z = zMAX) in the cross section. The elementary charge stands for letter e. 

Acknowledgment: The authors would like to thank Prof. S. Uno for his support to this work. This work has been supported by the science and technology program of Liaoning, the major industrial projects (Grant No. 2019JH1/1010022

Virtual Education Events at ESSDERC/ESSCIRC 2020

Given this uncertain situation, the organizing committee of ESSDERC/ESSCIRC 2020 in Grenoble and its Steering Committee, have decided to propose a new format for coming conference, which will include a NEW and Virtual Education Event series being developed for September 14th 2020 consisting of 13 educational sessions (workshops and tutorial) comprising invited presentations by leading academic and industrial experts and technologists. All related technical program details are also available online: https://www.esscirc-essderc2020.org/educationals

1. TUTORIAL | Quantum Computing: Myth or Reality?

Chairs: M. Vinet (CEA) and Farhana Sheikh (Intel)
Full content duration ~6h

2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems

Chairs: Matteo Perenzoni (FBK) and Albert Theuwissen (Harvest Imaging)
Full content duration ~6h

3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems

Chairs: Gabriel Molas (CEA) and Mahmut Sinangil (TSMC)
Full content duration ~6h

4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system)

Chairs: Nadine Collaert (imec) and Stefan G. Andersson (Ericsson)
Full content duration ~6h

5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN)

Chairs: Ionut Radu (Soitec) and Stefaan Decoutere (IMEC)
Full content duration ~6h

6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications

Chairs: Sylvain Clerc (ST) and Keith Bowman (Qualcomm)
Full content duration ~4h

7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions​

Chairs:  Andreas Burg (EPFL) and Marian Verhelst (KUL)
Full content duration ~6h

8. WORKSHOP | Ab-initio simulations supporting new materials & process developments

Chairs: Denis Rideau (ST) and Philippe Blaise (Silvaco)
Full content duration ~3h

9. WORKSHOP | RISC-V cooking session

Chairs: Bora Nikolic (BWRC)
Full content duration ~3h

10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data

Chairs:  Thierry Baron (CEA, LTM/UGA) and Audrey Dieudonné (UGA)
Full content duration ~3h

11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities

Chair: Philipp Häfliger (UiO)
Full content duration ~3h

12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization

Chair: Wladek Grabinski (MOS-AK) and Daniel Tomaszewski (ITE Warsaw)
Full content duration ~6h

13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future

Chairs: Dominique Thomas (ST), Klaus Pressel (Infineon), Rainer Pforr (Zeiss)
Full content duration ~6h

2020 IEEE ED Poland Chapter MQ

Date

2020-06-26

Location

Virtual

Region

IEEE Region 8 (Europe, Middle East and Africa)

Contact

Krzysztof Górecki – k.gorecki@we.am.gdynia.pl

Description

Distinguished Lecturer

Arokia Nathan - Oxide Electronics Univ. Cambridge (UK)

Mina Rais-Zadeh - MEMS development at JPL (US)

Benjamin Iniguez - Universitat Rovira i Virgili, Tarragona (SP)

Teodor Gotszalk - TU Wrocław (PL)

Mike Schwarz - MEMS Design & Simulation, Bosch (D)

REGISTER at the MQ site
https://eds.ieee.org/education/distinguished-lecturer-mini-colloquia-program/upcoming-dl-and-mq-events?eid=731&m=10e18da593444dc0cb20a2f377717f95