May 25, 2020

[paper] SPICE PCM Model

A SPICE Model of Phase Change Memory for Neuromorphic Circuits
Xuhui Chen1, Huifang Hu1, Xiaoqing Huang1, Weiran Cai2, Ming Liu3 (Fellow, Ieee), Chung Lam4,  Xinnan Lin1 (Member, IEEE), Lining Zhang5 (Senior Member, IEEE)
and Mansun Chan6 (Fellow, IEEE)
1The Shenzhen Key Lab of Advanced Electron Device and Integration, ECE, Peking University Shenzhen Graduate School, Shenzhen 518055 CN
2Institute of Microscale Optoelectronics, Shenzhen University, Shenzhen 518061 CN
3Key Laboratory of Microelectronics Devices and Integration Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, and the University of Chinese Academy of Sciences, Beijing 100049 CN
4Jiangsu Advanced Memory Technology Co., Ltd, Huaian 223302 CN
5School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, CN
6HKUST Shenzhen Research Institute, Shenzhen 518057, China, and Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, HK

doi: 10.1109/ACCESS.2020.2995907

Abstract: A phase change memory (PCM) model suitable for neuromorphic circuit simulations is developed. A crystallization ratio module is used to track the memory state in the SET process, and an active region radius module is developed to track the continuously varying amorphous region in the RESET process. To converge the simulations with bi-stable memory states, a predictive filament module is proposed using a previous state in iterations of nonlinear circuit matrix under a voltage-driven mode. Both DC and transient analysis are successfully converged in circuits with voltage sources. The spiking-timedependent- plasticity (STDP) characteristics essential for synaptic PCM are successfully reproduced with SPICE simulations verifying the model’s promising applications in neuromorphic circuit designs. Further on, the developed PCM model is applied to propose a neuron circuit topology with lateral inhibitions which is more bionic and capable of distinguishing fuzzy memories. Finally, unsupervised learning of handwritten digits on neuromorphic circuits is simulated to verify the integrity of models in a large-scale-integration circuits. For the first time in literature an emerging memory model is developed and applied successfully in neuromorphic circuit designs, and the model is applicable to flexible designs of neuron circuits for further performance improvements. 
FIG: Schematic diagram of commonly used PCM mushroom structure
URL: https://IEEExplore.IEEE.org/stamp/stamp.jsp?tp=&arnumber=9097232&isnumber=6514899

[paper] Graphene/4H-SiC/Graphene MSM UV-photodetector


An optimized Graphene/4H-SiC/Graphene MSM UV-photodetector operating
in a wide range of temperature 
H. Bencherif 1, L. Dehimi1 2, G. Messina 3, P. Vincent 4, F. Pezzimenti 3, F. G. Della Corte 3 1Laboratory of Metallic and Semiconductor Materials, University of Biskra, Biskra, DZ
2Faculty of Science, University of Batna 1, DZ
3DIIES, Mediterranea University of Reggio Calabria, Reggio Calabria, IT
4School of Electronics Engineering, KNU, 80 Daehakro, Buk-gu, Daegu, 702-701, KP

Abstract: In this paper, .an accurate analytical model has been developed to optimize the performance of an Interdigitated Graphene Electrode/p-silicon carbide (IGE/p-4H-SiC) Metal semiconductor Metal (MSM) photodetector operating in a wide range of temperatures. The proposed model considers different carrier loss mechanisms and can reproduce the experimental results well. An overall assessment of the electrodes geometrical parameters’ influence on the device sensitivity and speed performances was executed. Our results confirm the excellent ability of the suggested Graphene electrode system to decrease the unwanted shadowing effect. A responsivity of 238 μA/W was obtained under 325-nm illumination compared to the 16.7 μA/W for the conventional Cr-Pd/p-SiC PD. A photocurrent to- dark-current ratio (PDCR) of 5.75 × 105 at 300K and 270 at 500K was distinguished. The response time was found to be around 14 μs at 300K and 54.5 μs at 500K. Furthermore, the developed model serves as a fitness function for the multi objective optimization (MOGA) approach. The optimized IGE/p-4H-SiC MSM-PD design not only exhibits higher performance in terms of PDCR (7.2×105), responsivity (430A/cm2) and detectivity (1.3×1014 Jones) but also balances the compromise between ultrasensitive and high-speed figures of merit with a response time of 4.7 μs. Therefore, the proposed methodology permits to realize ultra-sensitive, high-speed SiC optoelectronic devices for extremely high temperature applications. 
FIG: a) Energy band diagram of Graphene/p-SiC/Graphene structure, b) Cross-sectional view of the suggested IGE/4H-SiC MSM UV-PD with interdigitated electrodes

Acknowledgments: This work was supported by DGRSDT Of Ministry of Higher education of Algeria. The work was done in the unit of research of materials and renewable energies (URMER).

Open Science Idea

Open Science Idea
2020 TEDxSkoltech Moscow
[full pdf: https://sci-hub.tw/alexandra/works/skoltech.pdf]

Talk  by Александра Элбакян, the Sci-Hub creator, at the TEDx conference at Uni Skoltech. The text transcript is given with  slides. All the video recording of that performance has been removed from TED website as the organizers referred to the fact that it violated some TED rules.


May 23, 2020

[PhD] Printed Inorganic Materials Electronics

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials
PhD Dissertation
Gabriel Cadilha Marques
Veröffentlicht am 30.04.2020
DOI: 10.5445/IR/1000118801

Abstract - The goal of this thesis is therefore to develop an inorganic printed electronics technology with corresponding modeling methodologies to capture device behavior for industry standard circuit simulators as well as circuit designs as building blocks for future applications. To reduce the high supply voltage requirements (~5V) in PE, alternative gating approaches for FETs are considered. One approach is to replace the dielectric with an electrolyte. Due to the formation of a Helmholtz double layer (HDL), a FET with a high gate-capacitance (~5 μFcm-2) is expected, reducing the voltage requirements to ~1V. By combining the indium oxide channel with the electrolyte-gating approach, high performance devices with low voltage requirements are available in PE.



May 19, 2020

[paper] Polymer Electrodes in Clinical EEG and MEG

Laura M. Ferrari, Usein Ismailov, Jean-Michel Badier, Francesco Greco and Esma Ismailova 
Conducting polymer tattoo electrodes in clinical electro- and magneto-encephalography
npj Flex Electron 4, 4 (2020)
Received: 17 October 2019; Accepted: 20 February 2020;
DOI: 10.1038/s41528-020-0067-z

Abstract - Temporary tattoo electrodes are the most recent development in the field of cutaneous sensors. They have successfully demonstrated their performances in the monitoring of various electrophysiological signals on the skin. These epidermal electronic devices offer a conformal and imperceptible contact with the wearer while enabling good quality recordings over time. Evaluations of brain activity in clinical practice face multiple limitations, where such electrodes can provide realistic technological solutions and increase diagnostics efficiency. Here we present the performance of inkjet-printed conducting polymer tattoo electrodes in clinical electroencephalography and their compatibility with magnetoencephalography. The working mechanism of these dry sensors is investigated through the modeling of the skin/electrode impedance for better understanding of the biosignals transduction at this interface. Furthermore, a custom-made skin phantom platform demonstrates the feasibility of high-density recordings, which are essential in localizing neuropathological activities. These evaluations provide valuable input for the successful application of these ultrathin electronic tattoos sensors in multimodal brain monitoring and diagnosis.

figure1
Fig: Temporary tattoo electrodes (TTEs) for EEG: a The layered structure of the temporary tattoo paper permits the release of the top film on which electrodes are fabricated. b Expanded view of an all-polymer printed TTE. c A TTE released on the scalp, in Oz position. d Close-in view of a TTE released on the scalp after 12 h from application. e Impedance recordings on the forearm using TTE and Ag/AgCl electrodes. 
Experiments involving human participants -Two able-bodied participants (one male and one female aged 33.5 ± 3.5 years old) free of any motor and neural disorders gave their informed consent and participated in this study. One participant performed the impedance recordings with the three diverse TTEs sets while another participant volunteered in the EEG/MEG evaluations with TTEs and Ag/AgCl electrodes. All experiments are performed following Timone hospital’s regulations regarding personal data protection. The experiment was conducted under conditions provided by French regulations.

Data Availability - The experimental data referenced in this text is available from the authors upon reasonable request.

#EU Parliament Strongly Recommends Developing and Using #opensource Software https://t.co/6HxdUaUHQK https://t.co/7czSKFmwh7


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May 19, 2020 at 10:00AM
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May 18, 2020

[paper] Novel Design and Optimization and the gm/ID Ratio

A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio
1Facultad de Ingeniería, Universidad Católica de Córdoba, Córdoba 5017 (AN)
2Service d’Électronique et Microélectronique, Université de Mons (UMONS), 7000 Mons (BE)
3Departamento de Electrónica, Instituto de Astrofísica de Canarias (IAC), 38200 La Laguna (SP)
* Author to whom correspondence should be addressed.
Electronics 2020, 9(5), 785; https://doi.org/10.3390/electronics9050785
Received: 31 March 2020 / Revised: 30 April 2020 
Accepted: 9 May 2020 / Published: 11 May 2020

AbstractThis work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in 65nm CMOS technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.
Figure: gm/ID versus iD

Acknowledgement - This research was funded by Universidad Católica de Córdoba (Argentina), the Walloon Region DGO6 BEWARE Fellowships Academia Programme (1410164-POHAR, cofunded by the European Marie Curie Actions), the Belgian FNRS (Fond National pour la Recherche Scientifique) and the Argentinean MINCyT (Ministerio de Ciencia y Tecnología).