[mos-ak] C4P: Special Issue of IEEE TED on Advanced Modeling of Power Devices and Their Applications

Call for Papers

For the Special Issue of

IEEE Transactions on Electron Devices 

On

Advanced Modeling of Power Devices and Their Applications

The special issue on "Advanced Modeling of Power Devices and Their Applications" is devoted to the research and development activities on power devices, the correlation of modeling approaches to the physics of power devices and in particular on emerging models of advanced power devices for power circuit applications. 

The importance of accurate circuit design with power devices is increasing according to the necessity of realizing efficient energy consumption. High-voltage MOSFETs are also utilized in all kinds of consumer electronics, and electric vehicles are controlled by IGBT circuit, where an urgent task is to achieve better energy control at about 1 kV bias condition. Accurate and even predictable models based on a close correlation to the important physical effects occurring in such power devices are therefore highly desired for precise circuit design. Presently many investigations are also undertaken intensively for new materials such as SiC and GaN replacing Silicon for extremely high voltage applications e.g. beyond 10 kV. A good understanding of the device operation under such extremely high bias conditions requires a lot physical analysis, and as a result leads to more effective utilization of these power devices. Together with the strong self-heating effect, the dynamically changing resistivity makes convergence in circuit simulation unstable. Techniques and physical analysis to overcome such problems are also urgently requested. 

Due to the wide range of covered bias conditions and the large variety of device structures applied, a lack of  communication occurs in the high-voltage community even though the basic tasks are the same. Therefore, the objective of this special issue is to bring together a diversity of R&D activities and advancements in the physical analysis and modeling of MOS-based power devices and other types of emerging power devices including Bipolar, Thyristor and Diode. Models for active and passive components integrated in advanced silicon as well as new material technologies, statistical modeling and mixed-mode simulation are also of special interest. 

The requirements for modeling high-voltage devices on the part of the circuit design community are now much more demanding due to urgent necessity to reduce energy consumption, where the high-voltage devices play an important role. Submissions should address advances in device characterization, physical models, as well as applications preferably but not limited to the following areas:

1. Compact modeling of power devices such as high-voltage MOSFETs, Bipolar, Thyristor and IGBT for 

circuit applications from a few volts up to beyond 10kV.

2. Modeling of passive elements such as Diode, Inductor, Resistor.

3. Investigations on new material such as SiC and GaN and their applications.

4. Circuit simulation for real applications of power devices together.

5. Investigation for computation efficiency for circuit simulation

Please submit manuscript by using the following:
http://mc.manuscriptcentral.com/ted

MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER

Paper Submission Deadline: July 15, 2012 

Scheduled Publication Date: February, 2013 

Guest Editors: 

Mitiko Miura-Mattausch, Hiroshima University, mmm@hiroshima-u.ac.jp  

Narain Arora, Silterra Malaysia, narain@silterra.com

Ehrenfried Seebacher,  Austriamicrosystems AG, ehrenfried.seebacher@austriamicrosystems.com

Samar K. Saha, SuVolta, Inc., samar@ieee.org

If you have any questions about submitting a manuscript, please contact:

Jo Ann Marsh (j.marsh@ieee.org)

IEEE EDS Publications Office

445 Hoes Lane Piscataway NJ 08854

Phone: +1 732 562 6855   Fax: +1 732 562 6831

http://www.ieee.org/

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5th "Micro&Nano2012" Kokkini Hani, Heraklion, 7-10 October 2012

Fifth International Conference "Micro&Nano2012"
on Micro - Nanoelectronics, Nanotechnologies and MEMs
Aquis Arina Sand Hotel, Kokkini Hani, Heraklion
7-10 October 2012

This is the first Micro&Nano conference, which will be organized at Heraklion, Grete, by members of the Micro&Nano society affiliated with the Foundation for Research and Technology (FORTH) and University of Crete. The conference will be co-chaired by Dr. Georgios Konstantinidis and Prof. Alexandros Georgakilas.

The Conference combines an extensive scientific programme including oral and poster sessions with exhibition and social events.

The Conference aims at gathering together in an interactive forum all scientists and engineers working in the challenging areas of micro/nano-electronic and optoelectronic/photonic devices, MEMs and circuits, as well as the enabling nanotechnologies of material growth, synthesis and processing. It aims to stimulate discussions on the last achievements and new developments in this rapidly evolving field.

One of the key objectives of the Conference is to promote collaboration and partnership between different academia, research and industry players. A one day workshop, presenting indicative cases and reviewing experiences and perspectives in these domains in Greece and elsewhere, will follow the conference [read more...]

The Scariest Graph

Posted from SemiWiki:

The Scariest Graph I've Seen Recently

by

Paul McLellan

Published on 06-18-2012 02:34 PM

10 Comments

Everyone knows Moore's Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.

But look at this graph:

This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel's server business since those have such high margins that they can probably live with a price that doesn't come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don't live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).

If this graph remains the case, then Moore's Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.

Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn't make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won't happen. And just like there is no business selling "microprocessor design tools" since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for "14nm design tools" to justify the investment.

So that's why this is the scariest graph in EDA.

[mos-ak] [2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

[2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the the technical program sponsor, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

Free on-line registration (open on June 18) 

http://www.mos-ak.org/bordeaux/registration.php

The terms of participation, intending participants and authors should also note the following dates: 

• Preannouncement - April 2012
• Call for Papers - May 2012
• Abstract submission deadline - July 2012
• On-line abstract submission (open on June 18):
• http://mos-ak.org/bordeaux/abstracts.php
• Final Workshop Program - Aug. 2012
• MOS-AK/GSA Workshop - Sept. 21, 2012 http://www.mos-ak.org/bordeaux/
• Morning Session
• Panel Discussion: "Status and Next Decade of European Compact Modeling"
• Poster Session 
• Afternoon Session

Speakers (tentative list): 

Prof. Maria Helena Fino, Universidade Nova Lisboa, P

Prof. Lidia Lukasiak, TU Warsaw, PL

Prof. Androula Nassiopoulou, IMEL Demokritos, GR

Prof. Elena Gnani, University of Bologna, I

Munira Raja. Uni. Liverpool, UK

Maria-Alexandra Paun, EPFL, CH

Sadayuki Yoshitomi, Toshiba, JP

Yogesh S. Chauhan, UC Berkeley, USA

Patrick Martin, Minatec, F

Daniel Tomaszewski, ITE Warsaw, PL

Further details and updates: <http://mos-ak.org/bordeaux/> 

Email contact: <workshops@mos-ak.org> 

- with regards - WG (for the MOS-AK/GSA Committee) 

––––––––––––––––––––––––––––––––––---------------- 

COMON Tranining Course Tarragona (SP) June 28-29, 2012

MOS-AK/GSA Bordeaux (F) Sept.21, 2012 

MOS-AK/GSA San Francisco, CA Q4 2012 

––––––––––––––––––––––––––––––––––---------------- 

Special IETE issue on Compact Modeling

Special IETE issue (May-June 2012 Volume 58; Issue 3 Page Nos. 179-242) on Compact Modeling: "Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits" is available on-line with following articles:

1. A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation p. 181
   Mike E Brinson, Stefan Jahn, H Nabijou
2. Aging Model for a 40 V Nch MOS, Based on an Innovative Approach p. 191
   Filippo Alagi, Roberto Stella, Emanuele Viganó
3. Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs p. 197
   Mike Schwarz, Thomas Holtij, Alexander Kloes, Benjamín Iñíguez
4. 2D Analytical Calculation of the Parasitic Source/Drain Resistances in DG-MOSFETs Using the Conformal Mapping Technique p. 205
   Thomas Holtij, Mike Schwarz, Alexander Kloes, Benjamín Iñíguez
5. RF Compact Modeling of High-voltage MOSFETs p. 214
   Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, Mingchun Tang
6. HSPICE Model of the Physical Resistor p. 222
   Petr Beták, Petr Zavrel
7. Enhanced Non-quasi-static Lauritzen Diode Model p. 226
   Lenka Sochová, Petr Beták, Ján Plojhár
8. Self-heating Parameter Extraction of Power Metal-oxide-silicon Field Effect Transistor Based on Transient Drain Current Measurement p. 230
   Risho Koh, Takahiro Iizuka
9. Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors p. 237
   Lorenzo Labate, Simona Angela Cozzi, Roberto Stella