Fwd: EUROSOI-ULIS 2026: Call for papers

On behalf of the Organizing Committee, it is our great pleasure to announce the 12th Joint EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS 2026), which will take place from May 20 to 22, 2026, in Granada, Spain.

This conference aims to bring together scientists and engineers in an interactive forum to discuss SOI technology and advanced microelectronic devices. A key objective is to foster collaboration and partnerships among academia, research institutions, and industry stakeholders in the field.

We warmly invite students and researchers from both academic and industrial backgrounds to submit their abstracts and join us in Granada. The conference offers an excellent opportunity to engage with colleagues, share knowledge, and experience the charm of this marvelous city.

We are also pleased to announce that the "IRDS & ISRDS workshop" will take place as a satellite event on 18–19 May at the same venue. This event will be an opportunity to dive into the heart of semiconductor innovation — to explore emerging directions in computing, and in materials and devices for computing — with expert-led sessions. Participation will be free of charge.

Abstract submission link: https://easychair.org/conferences?conf=eurosoiulis2026
Template: https://wpd.ugr.es/~eurosoiulis2026/wp-content/uploads/2025/07/EUROSOI-ULIS2026_Abstract_Template.docx

Important dates
- Abstract submission deadline: February 15, 2026
- Notification of acceptance: March 31, 2026
- Registration opening: March 1, 2026
- Early Bird Registration Deadline: April 20, 2026

Venue
The conference and the satellite workshop will be held in the Assembly Hall of the Facultad de Medicina of the Universidad de Granada (UGR). The Faculty of Medicine is located in the modern Parque Tecnológico de Ciencias de la Salud (PTS), a state-of-the-art campus that combines modern infrastructure with a comfortable, accessible environment, ideal for a scientific meeting like ours.

Selected papers will be published as 4-page letters in a Special Issue of Solid-State Electronics (Elsevier).

Two awards have been organized already:
- The "Androula Nassiopoulou Best Paper Award" attributed by the SINANO Institute.
- A best poster award attributed by Solid-State Electronics journal (Elsevier).

In addition to the technical program, we aim to offer an enriching cultural and historical experience for all attendees.

For more details, please see the attached call for papers or visit the conference website at:
https://eurosoiulis2026.ugr.es/

Future updates will also be posted on the website.

Best regards,
EuroSOI-ULIS 2026 Local Organizing Committee
eurosoiulis2026@ugr.es
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[paper] Single Event Upset in FINFET SRAM

SUN Qian¹²,, GUO Yang¹²*,, LIANG Bin¹², CHI Yaqing¹², TAO Ming³, LUO Deng¹², CHEN Jianjun¹², SUN Hanhan2, HU Chunmei¹2, FANG Yahao¹2, GAO Yulin¹2, XIAO Jing³

Process fluctuation influence on single event upset in sub-20 nm FinFET SRAM

中图分类号:TN405 文献标志码:A 文章编号:1001 - 2486 (2025)06 – 264 - 10 

1. College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China;
2. Key Laboratory of Advanced Microprocessor Chips and Systems, National University of Defense Technology, Changsha 410073, China;
3. College of Electrical and Information Engineering, Hunan University, Changsha 410082, China

Abstract: To investigate the process fluctuation influence on SRAM (static random-access memory) single event upset in sub-20nm FinFET (fin field-effect transistor) process, a high precision 3D TCAD model based on commercial process fluctuations was established, then simulated to find the FinFET SRAM single event upset threshold under different process corners. The simulation results show that the FinFET SRAM upset threshold has less variation induced by process corner fluctuation. Then, to understand the impact of specific process parameter fluctuations on the single event upset threshold, the process fluctuation factor impact on single event upset was discussed, including fin width, fin height, the oxide thickness and the work function fluctuation. The simulation results show that the first two factors did not affect the upset threshold, while the latter two factors caused slight fluctuations in the upset threshold. Significant reduction in the impact of process fluctuations on FinFET SRAM single event upset threshold is firstly found, which is of great significance for the development of highly consistent radiation hardened aerospace integrated circuits.  

Fig: Electron density snapshot when heavy-ion hit point A with 7 MeV · cm²/mg

[paper] Low-Frequency Noise in Single-Layer Graphene FETs

An extended low-frequency noise compact model for single-layer graphene FETs 

including correlated mobility fluctuations effect

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, and David Jiménez

https://arxiv.org/pdf/2512.08388

Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Bellaterra 08193 (SP)
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18011 Granada (SP)

Abstract: Correlated mobility fluctuations are considered in the physics-based carrier number fluctuation (ΔΝ) low-frequency noise (LFN) compact model of single-layer graphene field effect transistors (GFET) in the present study. Trapped charge density and Coulomb scattering coefficient ΔΝ LFN parameters are obtained after applying a parameter extraction methodology, adapted from conventional silicon technologies,to the linear ambipolar regions of GFETs. Appropriate adjustments are considered in the method according to GFETs’physical characteristics. Afterwards, Hooge mobility as well asseries resistance fluctuations LFN parameters can be extracted.The updated LFN model is validated with experimental data from various long and short-channel GFETs at an extendedrange of gate and drain bias conditions.

Fig: SID2/ID2 vs. VGS at 1 Hz for B (a) and A (b) -type RF GFETs with W=12μm and L=100nm

at VDS=60 mV. Markers: measurements, solid lines:model, dashed lines in (b): 

θint=0 V-1. Different colors represent different LFN contributions.

Acknowledgments: This work has received funding from the European Union’s Horizon2020 research and innovation programme under grant agreements NoGrapheneCore3 881603, from Ministerio de Ciencia, Innovación y Universidades under grant agreements RTI2018-097876-B-C21(MCIU/ AEI/ FEDER, UE), PID2021-127840NB-I00(MCIN/AEI/FEDER, UE), and CNS2023-143727 RECAMBIO (MCIN/AEI/ 10.13039 /501100011033). 

This work is also supported by the European Union Next Generation EU/PRTR research project.

[mos-ak] [Final Program] MOS-AK LatAm Webinar, Dec. 12, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LatAm Workshop

(online), Dec. 12, 2025

The End‑of‑Year MOS-AK Workshop/Webinar on Compact/SPICE Modeling will be held online on Dec. 12, 2025. We invite you to join this webinar to learn from the experts in Compact SPICE modeling, Verilog‑A standardization, and FOSS CAD/EDA IC design support for OpenPDKs, internationally, with particular focus on Latin America

Venue: MOS-AK LatAm (Webinar)
Online Webinar Access Link: https://meet.jit.si/MOS-AK_LA_2025

• Final Workshop Program: Dec. 12 2025
San Francisco, 09:00 - 11:00
Rio de Janeiro, 14:00 - 16:00
Geneve, 18:00 - 20:00

T_1	OpenPDK LatAm Krzysztof Herman IHP (D)
T_2	AI/ML-Driven Device Modeling for Advanced Nodes, RF and Power Applications Fahad Usmani Keysight Technologies (US)
T_3	Design and Integration of Multiple Open-Source Analog Circuits Fabricated in SKY130 Technology within Silicluster v2 Uriel Jaramillo Toral* Hector Emmanuel Muñoz Zapata and Susana Cisneros Ortega CINVESTAV (MX)
T_4	SemiCoLab, A Multi-Project ASIC Platform for Democratizing Chip Design Emilio Baungarten, Susana Ortega, Miguel Rivera, and Francisco Javier CINVESTAV (MX)
T_5	Building an Ecosystem Through IC Education in Colombia: A Model for Emerging Semiconductor Regions Juan Sebastián Moya Baquero SymbioticEDA
T_6	Silicon-Proven Learning With OpenPDKs and MPW Access for IC Education Eduardo Holguin Weber Universidad San Francisco de Quito (EC)
T_7	OpenPDK Mismatch Testchip Juan Pablo Martinez Brito CEITEC S.A. (BR)
T_8	Physics-Based Modeling and Charge Density Saturation in GaN/AlGaN MOS-HEMTs Ashkhen Yesayan, Farzan Jazaeri, Jean-Michel Sallese EPFL (CH)

W.Grabinski for Extended MOS-AK Committee

WG111225

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[paper] Noise Propagation and Statistic Variability in MOSFETs

Raphael Chatzipantelis, Loukas Chevas, Nikolaos Makris and Matthias Bucher

Noise Propagation and Statistic Variability in MOSFETs Using Probability Density Functions

Fluctuation and Noise Letters (Accepted Paper)

DOI: 10.1142/S0219477525400255

1) School of Electrical and Computer Engineering, Technical University of Crete, Chania 73100, Greece
2) Foundation for Research and Technology Hellas, Heraklion 70013, Greece,

Abstract: Probability density functions using stochastic methods are shown to be an effective tool in the context of MOSFET noise and variability modeling. These methods are employed here in the context of the charge-based EKV MOSFET model. As an example, a Gaussian noise density function applied at the gate or the source of a MOSFET causes a corresponding drain current noise density function, which may be expressed analytically as a function of inversion coefficient only. The same expression may be used to model drain current variability due to MOSFET parameters such as threshold voltage. Furthermore, the method is extended to variations of quantities such as transconductance and transconductance-to-current ratio. The method shows promise in variability modeling of MOSFETs and may complement traditional approaches.

FIG: Comparing the traditional ”small-signal” transconductance method with the stochastic PDF method for 𝑖𝑓, derived from the charge-based model, where in both cases the same noise (or variability) at the gate is applied (𝑉𝐺= 87mV, 𝜎𝑉𝐺=10mV), centered at 𝑖𝑓=2, showing slightly different mean and ±3𝜎 values, while the tail distributions differ significantly.

Acknowledgements: The authors gratefully acknowledge Dr. Predrag Habas from EM Microelectronic S.A. for valuable discussions and wafers for noise and statistical analysis. This work was partly funded by the European Union, and by Greek National funds, under the topic DIGITAL- Chips-2024-SG-CCC-1 - Competence Centers, Project No 101217803 - HCCC.