[mos-ak] IEEE SSCS-EDS South Brazil Chapter DL - IHP OpenPDK Initiative – Technology · Devices · Applications

The IEEE SSCS-EDS South Brazil Chapter, chaired by Juan Pablo Martinez Brito, PhD, to host Wladek Grabinski, PhD, a global expert in SPICE modeling and open-source IC design, for a Distinguished Lecture:

IHP OpenPDK Initiative – Technology · Devices · Applications

Date: August 13th, 2025

Time: 14h00 (GMT-3, Brasília)

IEEE SSCS-EDS South Brazil Chapter YouTube Channel

http://www.youtube.com/c/sscsedssouthbrazil

Dr. Grabinski will explore the growing role of FOSS CAD/EDA tools and OpenPDKs in strengthening the semiconductor ecosystem and enabling accessible IC design worldwide.

Thanks to the support of Unisinos, Federal University of Rio Grande do Sul, and UNIPAMPA Universidade Federal do Pampa RS, and to all the volunteers and engineers helping grow our regional chapter. Also, thank you to the chapter Board: Sandro Binsfeld Ferreira, Tiago Oliveira Weber, and Paulo César C. de Aguirre, and Professors Gilson Wirth and Sergio Bampi for the advice.

Looking forward to engaging with students, researchers, and professionals from across Brazil and beyond.

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South Brazil Section Jt. Chapter,SSC37/ED15

#OpenPDK #SPICE #CompactModeling #Semiconductors #IEEE #ICDesign #FOSS #AnalogDesign #PDK #CMOS #IHP #SkyWater #GF #EDA #SouthAmericaSemiconductors #MOSAK #EDS #SSCS #UFRGS #Unisinos #Unipampa

WG060825

Low Cost Open Source MPW Access with IHP 130nm BiCMOS OpenPDK

Low Cost Open Source MPW Access 

with IHP 130nm BiCMOS OpenPDK

Terms and conditions
The mentioned prices below refer to the open-source designs, where all the views are compatible with the open source EDA tools.

For customers who do not wish to disclose their IP, we offer participation in the OpenMPW program at a 20% discount off the regular price, as the wafers can be shared with other customers. The turn around processing time is approx. 6 months for SG13CMOS and 8 months for SG13G2. Our/IHP basic offer contains 20 bare die samples. It is also possible to rent the wafer for measurements. Packaging will be offered on request (additional fee can be applied). 

Request/reserve your MPW IC Chip area online

Date of the upcoming MPW tapeout:  Optional run in November 2025, SG13CMOS

Total amount used by all customers: tbd

Price per mm²:

SG13CMOS – the initial price is 1500 EUR/mm² and it will scale down to 1000 EUR/mm² 

if the total area requested by all customers will be higher than 150 mm²

SG13G2 – fully featured G2 with AL BEOL at approx. 2800 EUR/mm²

SG13G2 Technology overview:

• High speed SiGe HBT's featuring transit frequency (fT) of 350 GHz
• Low/High voltage CMOS devices
• 78 standard cells, IO-cells, a few fixed size SRAM
• Regular ESD diodes, NMOS clamps
• S-varicap
• Schottky diodes
• Polysilicon resistors, tap devices
• MIM capacitor
• 7 layer aluminium BEOL with 2 thick 3um top metal layers
• [NB] SG13CMOS does not provide HBT's

IHP-Open-PDK Overview

• Symbols for Xschem/Qucs-S
• Ngspice models
• Xyce models
• Klayout support for layout, PyCells, DRC and LVS
• Magic basic support (more to be finished until the end of the year)
• OpenROAD-flow-script support
• OpenEMS EM solver support
• Measurements RAW data in MDM format

Click here to open the IHP 130nm BiCMOS Open Source PDK documentation link

<https://ihp-open-pdk-docu.readthedocs.io/en/latest/index.html>

Click here to open the standard MPW price information

<https://www.ihp-microelectronics.com/services/research-and-prototyping-service/mpw-prototyping-service/schedule-price-list>

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[rsvNumerics] hands-on transistor sizing for analog ICs

rsvNumerics – info@rsvn.ch

Copyright © 2025 rsvNumerics – All Rights Reserved

rsvNumerics provides concepts, guidance and software tools for sizing transistors in integrated circuits with an easy-to-learn methodology. Whether you are a novice or an expert, you can benefit from our methodology and dimension your devices in no time, serving as a near-perfect starting point for your verification. Moreover, our methodology is not limited to a few predefined circuit topologies; it works for literally any circuit in any application.

Constant-𝑔𝑚 Biasing Circuit Example 

rsvNumerics in Circuit Design General, SizingTool

The schematic of the constant-𝑔𝑚 bias circuit is shown above. It consists of two cross-coupled current mirrors, where one of the source contacts, e.g. of an NMOS transistor, is degenerated by a source resistor. This results in a unique operating point of the circuit other than zero current, which defines the pass current in the two branches.

The corresponding settings of SizingTool 3 for transistor 𝑁𝑀0 and for transistor 𝑁𝑀1 are given in Fig above. Once the drain currents for a constant-𝑔𝑚 biasing block are known, we can use the information when designing any other transistor with derived source current. However, there its drain current has to be readjusted each time the process corner is changed to reflect for constant-𝑔𝑚 biasing, which is tedious, and is addressed by the current weighing option.

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[paper] Gradient Minimization in Layout Patterns for Analog Circuits

Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen

Gradient Minimization in Layout Patterns for Analog Circuits

Circuits, Systems, and Signal Processing. 1-22.

DOI: 10.1007/s00034-025-03158-x

1 Department of Electrical and Computer Engineering, Iowa State University, Ames, IA, USA

 

Abstract: In this paper, we present an algorithm to generate the layout of a pair of devices A and B for a given matching ratio r and total unit cell count N that minimizes the mismatch due to systematic gradient effects. The algorithm relies on simple reflections and rotations of an initial optimized pattern across 4 quadrants. The approach cancels all odd-order systematic gradients and minimizes 2nd order systematic gradients. The method can easily be extended to cancel higher-order even gradient effects. The validity of the proposed algorithm is demonstrated via numerical simulations. Additionally, an electrothermal simulation of a set of layouts is run to further validate the proposed layout generation scheme.

FIG: Layout of circuit design with heat sources and current sources 

for the optimal transistor array pattern.

[mos-ak] 一生一芯 2025 Summer Launch Conference

 One Student, One Chip

2025 Summer Launch Conference

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🗓 Conference Details

• Date & Time: July 21st (Monday), 14:30
• Location: Room 104, Mingde Campus, Shenzhen University, Nanshan District, Shenzhen, Guangdong Province
• Participation: Online registration open until July 19th, 23:59
• Live Stream: Bilibili Live Broadcast Link

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🎓 About the Project

The "One Student One Chip" (一生一芯, ysyx.org) program is an open-source, free, and public training platform aimed at developing full-stack engineers proficient in both hardware and software. It's designed for lifelong learners of all ages—from primary school to university—without limitations. Students are guided in designing and implementing a RISC-V CPU, using:

• Chisel (hardware description language)
• FPGA tools
• DK development environment

They explore concepts spanning:

• Digital logic
• RTL design
• Computer architecture
• Operating systems
• Compilers

Since its 2019 launch, the program has involved over 12,000 students, with backing from top universities including Tsinghua, Peking, and Fudan.

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🌟 Key Highlights for 2025

1. New teaching materials with a hierarchical learning model (EDCBA) to enhance learning efficiency
2. Post-course chip design program with ECOS Studio tools and open-source test platforms
3. Launch of MOLI Learning Platform, offering curated courses from universities like MIT, Tsinghua, and Peking University

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🏫 Supporting Institutions

• Tsinghua University
• Peking University
• Fudan University
• Zhejiang University
• Shanghai Jiao Tong University
• University of Science and Technology of China
• Harbin Institute of Technology
• National University of Defense Technology

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