Jul 1, 2025

[mos-ak] [OpenPDK] IHP Analog Academy

IHP Analog Academy


We, IHP Analog Academy, are excited to present this deep dive into analog, RF, and mixed-signal IC design, powered by open-source FOSS CAD/EDA tools and the IHP Open PDK.

This hands-on course is designed for engineers, researchers, and students eager to gain practical experience with the SG13G2 process at the 130nm technology node. Originally hosted on-site at IHP in Frankfurt (Oder), participants spent five intensive days exploring everything from fundamental analog simulation to advanced RF, 3D EM modeling, and mixed-signal integration. And now we're excited to release it to the open-source community!

The course covers:
- Bandgap reference design and simulation using the gm/Id methodology
- RF design of a 50 GHz Medium Power Amplifier with EM simulation
- Mixed-signal integration and verification of an 8-bit SAR ADC

Each module emphasizes a real-world design flow using tools like:
ngspice, Xyce, KLayout, OpenEMS, QUCS, and Python for data analysis.

Over time, we will expand the repository with:
- More modules
- Updated toolchain support
- Improvements to existing flows

Explore the IHP Open PDK:
- Open PDK GitHub Repository https://github.com/IHP-GmbH/IHP-Open-PDK 
- Interactive Help via ChatGPT https://chat.openai.com

Note: This is not an introductory IC design course. A basic understanding of electronics and microelectronics is assumed. We're proud to contribute this initiative to the community to help lower the barrier to IC design using open-source tools. We encourage contributions via GitHub Issues or Pull Requests! Your feedback and contributions, are welcome!

Lead Author: Phillip Ferreira Baade-Pedersen
Co-Author: Christian Wittke

The Development of this course is funded by the public German project FMD-QNC (16ME083) from BMFTR (Federal Ministry of Research, Technology and Space / Bundesministerium für Forschung, Technologie und Raumfahrt): https://www.elektronikforschung.de/projekte/fmd-qnc

#opensource #analog #mixedsignal #rf #design

Compact MOSFET Mechanical Stress Model

Bonev, Nikolay, Dirk Michael Nuernbergk, and Christian Lang
Inclusion of Mechanical Stress Effects in a Compact MOSFET Model
Science and Technology 28, no. 2 (2025): 138-149.
DOI: 10.59277/ROMJIST.2025.2.02

1 Melexis Bulgaria EOOD, Sofia, Bulgaria
2 Melexis GmbH Erfurt, Erfurt, Germany

Abstract: The analog performance of integrated circuits relies on stable parameters of its transistors. Mechanical stress changes the electronic properties of silicon and, therefore, also the device parameters. For circuit design, a good model of these effects is needed for a predictable and reliable function of the circuits. This article extracts the changes of various MOSFET parameters under effect of mechanical stress. A compact description of the stress effects is derived by applying tensors of piezo coefficients. The deviations are included in the physically based compact EKV model. A comparison with measured data shows that the stress effects are modelled correctly within a 10 % error margin.

Fig: Extraction setup for the specific current Is


Jun 21, 2025

Technical Lecture - the Celebration of FET100


You are all invited to register and attend the Technical Talks being organized by 
IEEE Electron Device Society (EDS) Delhi Chapter – India and IEEE EDS Community Engagement Ad-hoc Committee 
along with The National Academy of Sciences, India-Delhi Chapter; 
Science Foundation Committee of Deen Dayal Upadhyaya College, University of Delhi, New Delhi, INDIA

Kindly register for each talk separately and forward the email to your students and other colleagues.

Technical Lecture on June 23, 2025 @ 03:00 pm Italy time (GMT +2) i.e. 06:30 pm India Time (GMT +5.30)
The Field Effect Transistor - Evolution of the Modeling ApproachesMassimo Rudan, Professor EmeritusIEEE Life FellowDepartment DEI, University of BolognaSchool of Engineering, Bologna, Italy

Technical Lecture on June 25, 2025 @ 12:00 pm Aachen, North Rhine-Westphalia, Germany (GMT +2) i.e. 03:30 pm India Time (GMT +5.30).
A Brief History of Device Simulation for MOSFETsChristoph JungemannRWTH Aachen University

Technical Lecture on June 27, 2025 @ 02:00 pm (GMT+2) Time in Stockholm, Sweden i.e. 05:30 pm (GMT + 5:30) Indian Standard Time
Efficient Semiconductor Devices for a Sustainable FutureProfessor Mikael Östling, KTH Royal Institute of Technology, FIEEESchool of EECS, Stockholm, Sweden

Technical Lecture on June 30, 2025 @ 04:30 pm CET (GMT+2) Time in Madrid, Spain which shall be 08:00 pm Indian Standard Time (GMT +05:30)
History, evolution and perspective of Thin Film Transistor technologiesBenjamin IñiguezUniversitat Rovira i VirgiliTarragona, Spain

Technical Lecture on July 01, 2025 @ 09:00 am your time (GMT - 5) i.e. 07:30 PM Indian Standard Time (GMT +5:30)
Moore's Law and Radiation Effects on MicroelectronicsDaniel M FleetwoodOlin H. Landreth Professor of Engineering, Professor of Electrical and Computer Engineering, Professor of PhysicsVanderbilt University

Technical Lecture on July 01, 2025 @ 10:00 am (UTC - 5) i.e. 08:30 PM Indian Standard Time (GMT +5:30)
Perovskites – The New Frontier for Solar Photovoltaic Energy Conversion: Science and TechnologyVikram DalalFellow: IEEE, APS, AAASAnson Marston Distinguished ProfessorIowa State University, USA

Technical Lecture on 
July 2, 2025 @ 4:00 pm Italy time (GMT +2) i.e. 07:30 PM Indian Standard Time (GMT +5:30)
Nanoelectronics and Nanosystems Device Engineering for Sustainability, in the Energy and Variability Efficiency(E.V.E.) EraSimon Deleonibus, Life Fellow IEEE, Emeritus Fellow Electrochemical Society, Alternatives, Laboratoire d'Electronique et des Technologies de l'Information,(CEA-LETI), Grenoble, France.

Technical Lecture on
July 3, 2025 @ 10:30 am Italy time (GMT - 4) i.e. 08:00 PM Indian Standard Time (GMT +5:30)
Spin-field effect transistor – the unusual FETSupriyo Bandyopadhyay, Dept. of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA 23284

-- with regards -- Manoj Saxena

Professor Manoj Saxena | आचार्य मनोज  सक्सेना 
FNASc(IN), FIETE(IN), SMIEEE(USA)
Department of Electronics | इलेक्ट्रॉनिक्स विभाग
Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज
University of Delhi | दिल्ली विश्वविद्यालय
Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -, नई दिल्ली -११००७८
India | भारत

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Jun 20, 2025

[C4P] Micro Nano & Chips Tech 2025

 
12th International Conference on Micro-Nano & Chips Tech

Dear Colleagues,

You are cordially invited to participate in 

MICRO NANO & CHIPS TECH 2025

the 12th edition of the International Conference on Micro-Nanoelectronics, Nanotechnology and MEMS. 

The event will take place at the Cultural Center of Chania in Crete, Greece, from November 6 to 9, 2025.

Paper submissions are now open!

For more information, please visit the conference website: https://2025.micro-nano.gr/