[mos-ak] [C4P] 9th Sino MOS-AK Workshop Shenzhen, August 14-16, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

9th Sino MOS-AK Workshop Shenzhen

August 14-16, 2025

Announcement and C4P

The International MOS-AK Workshop will be held on Aug. 14-16th, 2025 on- the beautiful campus of the Southern University of Science and Technology (SUSTech), Shenzhen, China. With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. The workshop aims to strengthen a network and discussion forum for experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of analytical modeling, compact modeling, characterization and simulation techniques for advanced devices, circuits and technologies. In addition to regular papers, MOS-AK Shenzhen 2025 will host three tutorial/workshop sessions on advanced GaN device modeling and circuit design, cryogenic CMOS modeling and circuit design, and millimeter-wave radar applications.   

Paper Submission: Authors from both academia and industry are invited to submit technical papers describing original work and/or advanced practices and R&D projects

LINK: https://music-lab.feishu.cn/share/base/form/shrcng2ont1UhjEF0YZlOX1kZHb

(any related enquiries can be sent to music@sustech.edu.cn)

Online Registration is open (any related enquiries can be sent to music@sustech.edu.cn)

Important Dates:

• Manuscript submission deadline: 30th June 2025
• Notification of Acceptance: 10th July 2025
• Submission of final manuscript: 15th July 2025
• MOS-AK Workshop:  Aug. 14-16th, 2025

-- Xiaoguang Liu, SUSTech and W.Grabinski for Extended MOS-AK Committee

WG110625

 

[mos-ak] [2nd Announcement] MOS-AK Workshop, London, July 11, 2025

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

MOS-AK Workshop, London, July 11, 2025

2nd Announcement and C4P

The Summer MOS-AK Workshop on Compact/SPICE Modeling will take place on July 11, 2025, at London Met. The Conference Centre, room TM3-03, 166-220 Holloway Road, London. This event is coorganized by London MET with the technical cosponsorship of UK IETE and IEEE EDS. We invite you to join us for MOS-AK workshop and learn from the experts in the field of Compact SPICE modeling, Verilog-A standardization and FOSS CAD/EDA IC design support for OpenPDKs.

Planned Summer MOS-AK Workshop at London MET is a forum to strengthen a network and discussion among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology manufacturers, circuit designers, and CAD/EDA tool developers and vendors supporting foundry/fabless interface strategies with the focus on OpenPDKs (eg: Skywater/GF CMOS, IHP RF BiCMOS) 

Important Dates:

• 2nd Announcement: June 2025
• Final Workshop Program: June 30, 2025
• MOS-AK Workshop: July 11, 2025

MOS-AK/London Speakers Tentative List (alphabetic order):

• Phillip-Ferreira Baade-Pedersen; IHP
• Mike Brinson; London MET
• Patryk Golec; Uni. Paris-Saclay
• Wladek Grabinski, MOS-AK/IHP
• Krzysztof Herman; IHP
• Rohith-Karnati Penchala; Pragmatic Semiconductor Ltd.
• Radu Sporea; Uni. Surrey
• Bal Virdee; London MET

Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Free Registration is open (any related enquiries can be sent to registration@mos-ak.org)

W.Grabinski for Extended MOS-AK Committee

02062025

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[ICFOSS] Bridge Course for Eng/BSc Degree Aspirants

Bridge Course for Engineering/BSc Degree Aspirants - Season III

<https://icfoss.in/event-details/210>

ICFOSS is organizing a "Bridge Course" for Students who have completed their higher secondary education and aspires to pursue Engineering or BSc degrees in fields such as Computer Science, Electronics, Data Analytics, Physics, Mathematics and Statistics. The course will be conducted in two batches, scheduled from 26th to 31st May 2025 and 9th to 14th June 2025. This program mainly aims to provide them with the necessary knowledge, skills, and confidence to excel in various fields. It equips them with a strong foundation in Python programming and exposure to FOSS principles, setting them on a path for success and support during this transition period from school to college. This also aims to utilize this waiting period effectively by offering relevant educational activities and resources to help students to bridge the gap and stay engaged academically.

This is a combined course of Introduction to Python and Free and Open Source Software (FOSS), which is designed by ICFOSS to introduce students to Python programming and familiarize them with the concept and usage of free and open source software (FOSS). This program not only enhances their technical skills but also instills values of collaboration, knowledge sharing, and innovation that are essential in the field of technology. By the end of the course, students feels confident and well-prepared to tackle the challenges of college-level programming courses.

Objectives: Skill development and readiness for college- The course aims to develop essential skills required for success in college-level Engineering programs and BSc degrees in fields of Computer Science, Electronics, Data Analytics, Physics, Mathematics, and Statistics. It focuses on improving programming proficiency, logical reasoning, algorithmic thinking, and software development practices. The program also aims to support students, helping them stay motivated, engaged, and prepared for their upcoming BSc degrees or engineering programs.

Course Highlights: Live Classes, Structured curriculum by industry veterans, Customized for time flexibility, Custom learning path, Practical experience through simulations and project.

Mode of training: This training program is conducting in offline mode and our systematic approach includes skills assessment, intensive trainings and mentoring that helps valuable learning opportunities and unwavering support to students during this transition period.

Topics:

a) Introduction to Python : Introduction to Programming, Variables and Data Types, Control Flow and Decision Making, Lists, Tuples, and Dictionaries, Functions and Modules, File Handling, Object-Oriented Programming (OOP) Basics, Exception Handling, Deployment Using Flask, Working with External Libraries , Introduction to AI Concepts (Basics of AI, ML overview, Real-world Applications), Flask Project (Hands-on).

b) Free and Open Source Software: Introduction to FOSS, Linux Installation and Basics, Command-Line Basics, User and Group Management, Networking and Remote Access, System Services and Process Management, File System and Storage Management, Overview of FOSS Distros, Products, and Tools.

Target Audience: It is open to students who have completed their higher secondary education and aspires to pursue Engineering or BSc degrees in fields such as Computer Science, Electronics, Data Analytics, Physics, Mathematics, and Statistics.

Prerequisites: It is expected that students have a fundamental understanding of using computers.

Dates:

Name of Program	Dates	Time	Registration Fee
Batch 1	From 26th to 31st May 2025	10.00AM to 5.00 PM	Rs. 4,000/-
Batch 2	From 9th to 14th June 2025

Application Process: 

The number of participants is limited to 30 No.s per batch, on a first-come first-serve basis.

Course Duration: Total of 6 Days (6Hrs/Day)

Registration Fee: Rs. 4,000/-

Application deadline : 07th June 2025

For online payment, the bank accounts details of ICFOSS is provided below:

Account Name	ICFOSS
Account Number	67242303296
IFSC	SBIN0070737
Name of Bank	State Bank of India
Branch	Technopark, Thejaswini, Thiruvananthapuram

For Registration, follow: https://applications.icfoss.org/bridge-course-2025/
Please contact +91 7356610110 | +91 471 2413012 /13 /14 | +91 9400225962
between 10:00-17:00 hrs) for further clarifications.

EDS SCV/SF Hybrid DL Event on Friday June 27

IEEE SCV-SF EDS Distinguished Lecturer Event:

Friday, June 27th, 2025 – 11:30AM to 1PM (PDT)

Dr. Xing Zhou: Monolithic Co-integration of III-V Materials

into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter will host a hybrid Distinguished Lecturer event on June 27th at noon PST by Dr. Xing Zhou on the topic of "Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits." The event will be held at Plug and Play Tech center in Sunnyvale, CA and also on zoom. The zoom meeting link will be sent to registered attendees a few days before the event. Event information below. The ticket options for both "In-person" and "On-line" attendance are available. Please select the appropriate ticket so we can get an accurate headcount for ordering food for the event.

Please register here: Link

Imran Bashir

SCV-SF EDS Chair

Distinguished Lecturer Event: Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Dr. Xing Zhou.

When: Friday, June 27th, 2025 – 11:30AM to 1PM (PDT)

11:30AM - 12PM: Networking / Food

12PM-12:45PM: Lecture

12:45PM-12:55PM: Q&A

1PM Adjourn

Where: Rappi Room, Plug and Play Tech Center

440 N Wolfe Rd, Sunnyvale, CA 94085

This is an hybrid event and attendees can participate via Zoom. The Zoom meeting link will be sent a few days before the event to registered attendees.

Contact: ieeescveds at gmail.com

Speaker: Dr. Xing Zhou

Abstract: As Moore's Law is slowing down and eventually approaching an end for conventional CMOS, new platforms for producing circuit-level innovation are desired. At the same time, it is not desirable to throw away the existing Si-CMOS infrastructure to start new. This talk presents an overview of the 10-year research program, which is a "vertical" innovative platform by "inserting" III-V layers into a conventional Si-CMOS foundry process. The talk also presents a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technology developed for future heterogeneous integrated circuits. The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si monolithically co-integrated technology.

Speaker Bio: Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore from 1992 to 2024. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His research at NTU mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs. He has given more than 150 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. Dr. Zhou was the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference (2002–2018). He was an editor for the IEEE Electron Device Letters (2007–2016), a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and a member of the Modeling & Simulation subcommittee for IEDM (2016, 2017). He was an Elected Member-at-Large of EDS Board of Governors (2004–2009; 2011–2016) and served as Vice-President for Regions/Chapters (2013–2015). He has been an EDS Distinguished Lecturer since 2000. He is a Life Senior Member of the IEEE and currently serves as chair for the RS/EPS/EDS Singapore Joint Chapter.

RC and RL circuits and smartphones

Marciano Santamaría Lezcano1 E S Cruz de Gracia2, Lucio Strazzabosco Dorneles3 

and Noriel Correa1

Frequency effect on reactance in RC and RL circuits - a smartphone approach

Phys. Educ. 60 (2025) 035033 (8pp) 

DOI: 10.1088/1361-6552/adc8ec

1 Universidad de Panamá, Departamento de Física, Centro de Investigación con Técnicas Nucleares, Panama City, Panama
2 Universidad Tecnológica de Panama, Centro Regional de Veraguas, Veraguas, Panama
3 Universidade Federal de Santa Maria, Santa Maria, RS, Brazil

emails: evgeni.cruz@utp.ac.pa, marciano.santamaria@up.ac.pa, lucio.dorneles@ufsm.br and noriel.correa@up.ac.pa

Abstract: This paper presents a new and successful methodology for determining the frequency effect on capacitive and inductive reactance in RC and RL series circuits. The key feature in our approach is the practical use of a smartphone as a signal generator and an oscilloscope in alternating current circuits. By generating and visualising the signal using free software applications, we could observe the capacitor's and the inductor's response to frequency variations between 0.1 and 5.0 kHz. The experimental data, analysed within the theoretical capacitive and inductive reactance model, shows excellent agreement with the expected values, instilling confidence in the reliability and feasibility of our methodology. This alignment between experimental and theoretical data not only underscores the potential use of smartphone technology in capacitive and inductive reactance studies but also highlights the practicality of our approach to experimental analysis in science and engineering.

FIG: The connection diagram of (a) RC and (b) RL circuits

shows smartphones working as signal generators and oscilloscopes.

Data availability statement: All data that support the findings of this study are included within the article (and any supplementary files).

Acknowledgments: The authors, M. Santamaría and N. Correa would like to thank the Development Bank of Latin America and the Caribbean (CAF) for financially supporting the Renovation Program of the Faculty of Natural and Exact Sciences and Technology of the University of Panama, which includes the acquisition of instruments used in this research. E S Cruz de Gracia, an SNI member, thanks the Secretaria Nacional de Ciencia, Tecnología e Innovación (SENACYT) for its support. Finally, L.S. Dorneles acknowledges support from CNPq Grant 308277/2021-0.