[workshop] FreeCAD 3D parametric modeler

PSG COLLEGE OF TECHNOLOGY, COIMBATORE

9 DECEMBER, 2023

About the FreeCAD

FreeCAD is a general purpose open source parametric 3D CAD modeller. FreeCAD is aimed directly at mechanical engineering and product design but, being very generic, also fits in a wider range of uses around engineering, such as architecture, finite element analysis, 3D printing, and other tasks. FreeCAD offers tools to produce, export and edit solid, full-precision models, export them for 3D printing or CNC machining, create 2D drawings and views of your models, perform analyses such as Finite Element Analyses, or export model data such as quantities or bills of materials. FreeCAD features tools similar to other popular CAD packages and therefore also falls into the category of CAD, PLM, CAx, CAE and BIM. It is a feature based parametric modeler with a modular software architecture, making it possible to provide additional functionality without modifying the core system. As with other CAD modelers, it has many 2D components in order to sketch planar shapes or create production drawings. FreeCAD is also fundamentally a social project, as it is developed and maintained by a community of developers and users united by their passion for FreeCAD. In precise FreeCAD is:

• Made to build for the real world
• A powerful solid-based geometry kernel
• A wi(l)dly parametric environment
• File formats frenzy
• A parametric constraints-based 2D sketcher
• A large (and growing) multi-specialty ecosystem

About the Workshop 

The workshop will be conducted through spoken tutorial videos of 10 minutes duration. After the workshop, a link for the video tutorials will be shared to the participants for further learning. As it is an open source software, FreeCAD can be used free of cost for educational and industrial design purposes. Participants of this workshop can install this software on their laptop during this workshop and take it with them. Target participants of this workshop include: practicing engineers, faculty members, research scholars and students.

Registration details
The registration fee for the participants (Inclusive of GST) :

• Faculty members / Students / Research Scholars : Rs. 900/-
• Industry participants : Rs.1200/-

No TA/ DA/ ACCOMMODATION will be provided. Payment of registration fee for the workshop can be made through online mode

https://forms.gle/xqcQLSTnJcYLK2DNA

Last date for registration: November 25, 2023

For any queries, contact

The Organizing Secretaries,

FreeCAD Workshop, PSG College of Technology,

Peelamedu, Coimbatore-641004

email : vsk.amcs@psgtech.ac.in / mrp.prod@psgtech.ac.in

Mobile : 9952418357

[paper] Surface-Potential-Based Compact Modeling

M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch, and S. Saha

Evolution of Surface-Potential-Based Compact Modeling

IEEE EDS NEWSLETTER

OCTOBER 2023 VOL. 30, NO. 4 ISSN: 1074 1879

Abstract: Conventionally, a compact model of an electronic device is developed for utilization in circuit simulation. This means that the main task of the compact model is to accurately describe the characteristics of a device as a function of the applied voltages by simple equations in order to predict the performance of circuits using this device with sufficient precision. This overview article focuses on the compact modeling of the metal-oxide-semiconductor field-effect transistor (MOSFET)-device structure, which has the largest variety of applications. However, the modeling methodology is valid for any type of transistor or electronic device. The development of the compact modeling approach, based on the potential distribution induced within a transistor, is reviewed. The purpose of a compact model is to describe the transistor characteristics in a simple but accurate way, to enable correct circuit-performance prediction. Therefore, the basic physics of observed phenomena must be modeled by simplified and yet physically correct equations. To meet such requirements, potential-based modeling is a natural fit. A compact model and TCAD are both based on the same transistor equations. The difference is that TCAD considers the distribution of all physical quantities within a device, and a compact model integrates these distributions to calculate transistor characteristics at its nodes. The shortcomings of resulting simplifications, introduced for analytical integration, can be examined using TCAD, to identify observed phenomena still missing in the compact modeling. In this way, compact modeling is performed by learning from measurements macroscopically and from TCAD microscopically.

Fig: Schematic of a HV LDMOS FET (top) 

and its potential distribution (bottom)

[paper] ChipNeMo

Mingjie Liu, Teo Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian LiangJonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany Kishor Kunal, Xiaowei Li, Hao Liu, Stuart Oberman, Sujeet Omar, Sreedhar Pratty, Ambar Sarkar Zhengjiang Shao, Hanfei Sun, Pratik P Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren

ChipNeMo: Domain-Adapted LLMs for Chip Design

arXiv:2311.00176 [cs.CL]

DOI: 10.48550/arXiv.2311.00176

* NVIDIA

Abstract: ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: custom tokenizers, domain-adaptive continued pretraining, supervised fine-tuning (SFT) with domain-specific instructions, and domain-adapted retrieval models. We evaluate these methods on three selected LLM applications for chip design: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. Our results show that these domain adaptation techniques enable significant LLM performance improvements over general-purpose base models across the three evaluated applications, enabling up to 5x model size reduction with similar or better performance on a range of design tasks. Our findings also indicate that there’s still room for improvement between our current results and ideal outcomes. We believe that further investigation of domain-adapted LLM approaches will help close this gap in the future.

Fig: LLM script generator integration with EDA tools

Acknowledgements: The authors would like to thank: NVIDIA IT teams for their support on NVBugs integration; NVIDIA Hardware Security team for their support on security issues; NVIDIA NeMo teams for their support and guidance on training and inference of ChipNeMo models; NVIDIA Infrastructure teams for supporting the GPU training and inference resources for the project; NVIDIA Hardware design teams for their support and insight.

MINIMAL

"Minimal Fab Promotion Organization" (MINIMAL) aim is to establish a completely new production method called this minimal fab and initiating a process revolution in Japan. The mission is to further expand the application fields of Minimal Fab as the only organization in the world to support the spread and development of high-mix low-volume of microdevices such as semiconductors and MEMS as innovative industrial systems. We are aiming to become an innovation platform to promote small businesses using the Minimal Fab through collaboration among various industries such as various toolmakers, materials, parts and device users [ read more...]

INUP-i2i - Idea to Innovation

INUP-i2i

Indian Nanoelectronics Users’ Programme

Idea to Innovation

Ministry of Electronics and Information Technology – MeitY, with the long-term vision of improving skilled manpower in the areas of micro and nanoelectronics had established the Indian Nanoelectronics Users’ Programme (INUP) about a decade back. The initiative enabled the researchers to travel from the country's remotest locations and implement their ideas at the state-of-art nanofabrication and characterization facilities available at Centres of Excellence established at the Indian Institute of Science Bangalore and Indian Institute of Technology Bombay. Over the years, the brand INUP has caught the imaginations of the scholars from numerous technical colleges and universities who could not afford to have such facilities to perform research. The user base grew from the first (2008-2014) to the second 2014-2019) phases of implementation. Thousands of researchers have received hands-on training at various levels in such state-of-art facilities in the multi-disciplinary areas of micro/nanoelectronics. Hundreds of them could implement their research ideas and produce scientific and technological outputs. The initiative resulted in unprecedented benefits to the budding scholars in developing cutting-edge research prototypes, which was found to be way beyond the traditional soft-teaching pathways through textbook knowledge. The initiative also helped the participants write and submit research proposals, budget the same, implement ideas at the ground level, schedule project work, submit project reports, prepare scientific manuscripts, and develop the devices.

INUP-i2i OBJECTIVES

• Enhance R&D ecosystem in the area of nanoelectronics by leveraging the Nano centres established by MeitY.
• Conduct training/workshops in the field of Nanoelectronics for wider dissemination of knowledge.
• Support the exploratory and innovative research for development of technologies in Nanoelectronics
• Mentor startups for commercialization of nanotechnologies.
• Conduct Hackathons/Grand Challenge targeting societal applications to develop Nano engineered solutions.

Hands-on training workshop are organized on the following different themes:

• Sensors and Microfluidics
• Organic Electronics
• 2D materials and devices
• Logic & Memory Devices
• Spintronics
• Compound Semiconductor Devices
• Photovoltaics
• MEMS

[read more...]