[paper] Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs

Sujit K. Singh, Sumreti Gupta, Reinaldo A. Vega* and Abhisek Dixit

Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model

in IEEE Electron Device Letters

DOI: 10.1109/LED.2022.3158495.

  

 Indian Institute of Technology, New Delhi (IN)

*IBM Research, Albany, NY (USA)

Abstract: In this letter, we have proposed modifications to the existing BSIM-CMG compact model to enhance its ability to model the behavior of short channel bulk FinFETs (both n and p-type) from room temperature down to cryogenic temperatures (10K). The proposed model is highly accurate in capturing the subthreshold swing, threshold voltage, and effective mobility trends observed in FinFET cryogenic operation. For efficient optimization of the proposed model parameters, we have proposed an adequate modeling strategy. We have compared convergence time between the existing BSIM-CMG model and the proposed model by simulating a reasonably large circuit using pseudo-inverters.

Fig (a) TEM image of the fin cross-section (b) Measured device layout-related parameters 

[paper] Ultra-Low-Power Imaging System

Andrea Bejarano-Carbo, Hyochan An, Kyojin Choo, Shiyu Liu, Dennis Sylvester, 

David Blaauw and Hun-Seok Kim, 

Millimeter-Scale Ultra-Low-Power Imaging System for Intelligent Edge Monitoring

inyML Research Symposium’22, March 2022, San Jose, CA

rXiv:2203.04496v1 [eess.SP] 9 Mar 2022

  

University of Michigan, Ann Arbor, Michigan, USA

ABSTRACT Millimeter-scale embedded sensing systems have unique advantages over larger devices as they are able to capture, analyze, store, and transmit data at the source while being unobtrusive and covert. However, area-constrained systems pose several challenges, including a tight energy budget and peak power, limited data storage, costly wireless communication, and physical integration at a miniature scale. This paper proposes a novel 6.7×7×5mm imaging system with deep-learning and image processing capabilities for intelligent edge applications, and is demonstrated in a home-surveillance scenario. The system is implemented by vertically stacking custom ultra-low-power (ULP) ICs and uses techniques such as dynamic behavior-specific power management, hierarchical event detection, and a combination of data compression methods. It demonstrates a new image-correcting neural network that compensates for nonidealities caused by a mm-scale lens and ULP front-end. The system can store 74 frames or offload data wirelessly, consuming 49.6μW on average for an expected battery lifetime of 7 days.

Fig: Imager system cross-section

Acknowledgments:The authors would like to thank Sony Semiconductor Solutions Corp./Sony electronics Inc. for supporting this work.

Faster #analog #computer could be based on mathematics of complex systems

Faster #analog #computer could be based on mathematics of complex systems https://t.co/A0iTUZK2U9 #semi https://t.co/Cn0cfGZHqZ

— Wladek Grabinski (@wladek60) Mar 14, 2022

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from Twitter https://twitter.com/wladek60

March 14, 2022 at 05:57PM
via IFTTT

Creating sub-1-nm gate lengths for MoS2 transistors

Creating sub-1-nm gate lengths for MoS2 transistors https://t.co/7E4V3Bp3Bz #semi https://t.co/1pwI2wUajO

— Wladek Grabinski (@wladek60) Mar 14, 2022

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from Twitter https://twitter.com/wladek60

March 14, 2022 at 05:50PM
via IFTTT

[mos-ak] [2nd Announcement and C4P] Spring MOS-AK Workshop on April 1, 2022 (online)

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

Spring MOS-AK Workshop

April 1, 2022 (online)

2nd Announcement and C4P

Together with local online host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the Spring MOS-AK Workshop which will be organized as the virtual/online event on April 1, 2022, between 2:00pm - 6:00pm (CET) providing an opportunity to meet with modeling engineers and researchers from Europe and Latin America. 

Upcoming online Spring MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies

Online Abstract Submission to be open (any related enquiries can be sent to absttracts@mos-ak.org)

Online Event Registration to be open (any related enquiries can be sent to registration@mos-ak.org)

Important Dates: 

• Call for Papers: Feb. 2022
• 2nd Announcement: March 2022
• Final Workshop Program: March 22, 2022 
• Spring MOS-AK Workshop: April 1, 2022

W.Grabinski for Extended MOS-AK Committee

WG090322

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