Feb 3, 2022

Aramco partners with Japan’s Yokogawa to localize chip manufacturing in Saudi Arabia



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February 03, 2022 at 05:35PM
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[ESSDERC/ESSCIRC 2022] Call for Papers

Paper submission is open!
Submission deadline: Apr 12, 2022 23:59 (GMT -0700)
Decision notification: May 31, 2022 23:59 (GMT -0700)

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

PAPER SUBMISSION
Manuscript guidelines as well as instructions on how to submit electronically will be available on this website. Papers must not exceed four A4 pages with all illustrations and references included.
THE PAPERS SUBMISSION DEADLINE: APRIL 12, 2022

Papers submitted for review must clearly state:
•The purpose of the work
•How and to what extent it advances the state-of-the art
•Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 31 May 2022.

At the same time, the complete program will be published on the conference website. A binary feedback (accepted/rejected) with no comments will be provided to the authors. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

[paper] Transistor Modelling for mm-Wave Technology Pathfinding

B.Parvais1, R. ElKashlan1, H. Yu, A. Sibaja-Hernandez, B. Vermeersch, V. Putcha, P. Cardinael2, R. Rodriguez, A. Khaled, A. Alian, U. Peralagu, M. Zhao, S.Yadav, G. Gramegna, J. Van Driessche, N. Collaert
Transistor Modelling for mm-Wave Technology Pathfinding
SISPAD, 2021 
DOI: 10.1109/SISPAD54002.2021.959253
   
* imec, Kapeldreef 75, 3001 Leuven, Belgium
1 also with Vrije Universiteit Brussels, 1050 Brussels, Belgium
2 also with UCLouvain, Louvain-la-Neuve, Belgium


Abstract: A review of the modelling requirements to establish a Design-Technology Co-Optimization loop for mmWave Front-End Modules is presented. The example of GaN/Si technology is detailed, and recent modeling developments are explained.

Fig: The RF-DTCO loop concept: from device modeling
and exploration to benchmark circuits.







[paper] Piezosensitive Pressure Sensor Chip

Mikhail Basov
Pressure sensor chip utilizing electrical circuit of piezosensitive differential amplifier with negative feedback loop (PDA-NFL) for 5 kPa
XI International Scientific and Technical Conference 
"Micro-, and Nanotechnology in Electronics", 
Elbrus, Russia; June 2021
  
Dukhov Automatics Research Institute VNIIA, Moscow

Abstract: High sensitive (S=11.2±1.8 mV/V/kPa with nonlinearity error 2KNL=0.15±0.09 % /FS) small-sized (4.00x4.00 mm2) silicon pressure sensor chip utilizing new electrical circuit for microelectromechanical systems (MEMS) in the form of differential amplifier with negative feedback loop (PDA-NFL) for 5 kPa differential was developed. The advantages are demonstrated in the array of output characteristics, which prove the relevance of the presented development, relative to modern developments of pressure sensors with Wheatstone bridge electrical circuit for 5 kPa range.

Fig: a) Pressure sensor chip, b) its assembled structure




Feb 2, 2022

[EZMod3D] Comparing inductance extraction to measurement

EZMod3D is a division of EASii IC, which develops a 3D multi-domain physical simulation software solution (also called 3D field solver) mainly developed to process the design of integrated circuits (ASICs), printed circuit boards (PCBs) and both at the same time (CoDesign). EZMod3D was developed on the basis of an innovative solver enabling a fast simulation. This technology has allowed intensive use internally at EASii IC, targeting the requirements of R&D project: reducing iterations between design and manufacturing.

Very simple, you just need to start with your input data
  • GDS2 file, OASIS database, LEF / DEF (ASIC) or Gerber (PCB) or DXF (Packaging)
  • Technological file or materials description
  • The position of the potentials or flows to be applied
  • In pre-sizing step, you can sketchup using advanced user intergrated matrial library
FIG: An inductor, its 3D EZMod3D simulation and LCR measurements. EZMod3D now extracts inductance values and shows good agreement with measurements.
Measured value is 477nH; close to the simulated 481nH)