[paper] Implementation of Low Power Inverter using JL DG TFET

Sabitabrata Bhattacharya and Suman Lata Tripathi

Implementation of Low Power Inverter 

using Si1‑xGex Pocket N & P‑Channel Junction‑Less Double Gate TFET

Silicon, Springer Nature B.V. 2021

Received: 19 October 2021 / Accepted: 16 December 2021

DOI: 10.1007/s12633-021-01628-w

  

* School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

Abstract: In this paper tunnel field effect transistor is reintroduced as an efficient low power replacement of MOSFET. The main draw- backs of TFET devices, like low ON-state current and low ION/IOFF ratio, are removed by structural and material modifica- tions. The proposed device is named junction-less double gate TFET or JL DGTFET. The junction-less attribute is used to reduce fabrication complexity, double gate is used to have better control over channel conduction and enhance drive current, high k gate dielectric and high work function gate metal is used to increase ON current. Low band gap Si1-xGex pocket is used near source end of the device to further improve performance. Four-fold optimization of the device is done along with temperature analysis to propose the best possible structure and dimensions. The proposed junction-less DGTFET was found to show huge performance improvement in ION/IOFF (of the order of 1011) and short channel parameters (SS = 63.5 mV/dec- ade, DIBL = 22.2 mV/V) over existing TFET devices. Both N & P-channel of the device is implemented with the optimised values on 18 nm technology node. Finally, an inverter circuit using both the N & P-channel devices is implemented following the CMOS compatible structure, and it is found to give very good results at low power.

Fig: Design of inverter circuit using n-JL DGTFET and p- JL DGTFET

Acknowledgements: The authors acknowledge for the support and lab facility provided by department of VLSI design, School of Electronics and Electrical Engineering, Lovely Professional University, Punjab India.

American chip-making giant Intel is a shadow of its former self

[Naveed Sherwani] American chip-making giant Intel is a shadow of its former self Details: https://t.co/79n7d6rQJI #semi https://t.co/mkWoP5ms5t

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Hdev: Open-Source SiGe and III-V HBT TCAD Simulator

Hdev: https://gitlab.com/metroid120/hdev_simulator

Hdev has been started as a TCAD simulator by Martin Claus at TU Dresden (initially named COOS). Hdev (heterostructure device) is a TCAD simulator focused on 1D and 2D simulations of HBTs. The purpose of Hdev is to allow easy technology analysis and optimization of heterostructure semiconductor devices. Later it has been adopted by Sven Mothes who also used it for CNTFET simulations. Then, it has been applied to organic semiconductors by Markus Müller in his bachelor and diploma theses, where the initial 2D drift-diffusion solver has been implemented. For his dissertation on InP HBTs, Markus Müller later created a fork of COOS aimed at HBT simulation. The fork has been renamed Hdev (heterostructure device) for highlighting the new focus of the software. Hdev is now applied to SiGe and III-V HBTs by Markus Müller in the scope of his PhD thesis.

Hdev Features:

• true 1D simulations => time efficient
• box discretization => easy to use
• semiconductor alloys => SiGe and III-V HBTs
• DC, AC and transient analysis
• augmented DD equation
• degenerate semiconductor statistics
• read and write hdf5 files
• GPL license

Figure 1: (left) vertical profile of the node three HBT and (right) transfer characteristics of the HBT from 1D energy-transport simulations at VBC = −0.7 V at 300 K.

The world needs more skilled semiconductor workers

[https://t.co/22F0rWWNRA] The world needs more skilled semiconductor workers #semi https://t.co/yKPWleJvnJ

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[paper] Embedded CMOS SOI UV Sensors

Michael Yampolsky, Evgeny Pikhay and Yakov Roizin

Embedded UV Sensors in CMOS SOI Technology

Sensors 2022, 22(3), 712;

DOI: 10.3390/s22030712

   
Tower Semiconductor, Migdal Haemek 2310502, Israel

Abstract: We report on ultraviolet (UV) sensors employing high voltage PIN lateral photodiode strings integrated into the production RF SOI (silicon on isolator) CMOS platform. The sensors were optimized for applications that require measurements of short wavelength ultraviolet (UVC) radiation under strong visible and near-infrared lights, such as UV used for sterilization purposes, e.g., COVID-19 disinfection. Responsivity above 0.1 A/W in the UVC range was achieved, and improved blindness to visible and infrared (IR) light demonstrated by implementing back-end dielectric layers transparent to the UV, in combination with differential sensing circuits with polysilicon UV filters. Degradation of the developed sensors under short wavelength UV was investigated and design and operation regimes allowing decreased degradation were discussed. Compared with other embedded solutions, the current design is implemented in a mass-production CMOS SOI technology, without additional masks, and has high sensitivity in UVC.

Fig: (a) A string of PIN photodiodes connected in series by silicide N+, P+, and iSi regions. The diodes are connected by butted silicide. The schematic cross section shows only three connected in series PIN diodes. (b) Cross section of a lateral PIN diode with contacts.