Oct 28, 2021

#Apple joins as first public partner in new #imec research program



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Oct 27, 2021

[paper] Transistors Based on Lateral PtSe2 Heterostructures

Gaetano Calogero*, Damiano Marian, Enrique G. Marin**, Gianluca Fiori 
and Giuseppe Iannaccone
Physical insights on transistors based on lateral heterostructures 
of monolayer and multilayer PtSe2 via Ab initio modelling of interfaces
Sci Rep 11, 18482 (2021)
DOI: 10.1038/s41598-021-98080-y
  
Dipartimento di Ingegneria dell’Informazione, Università di Pisa  (I)
*Consiglio Nazionale delle Ricerche, Istituto per le Microelettronica e Microsistemi (I)
**Dipartimento Electronica, Facultad de Ciencias, Universidad de Granada (SP)

Abstract: Lateral heterostructures (LH) of monolayer-multilayer regions of the same noble transition metal dichalcogenide, such as platinum diselenide (PtSe2), are promising options for the fabrication of efficient two-dimensional field-effect transistors (FETs), by exploiting the dependence of the energy gap on the number of layers and the intrinsically high quality of the heterojunctions. Key for future progress in this direction is understanding the effects of the physics of the lateral interfaces on far-from-equilibrium transport properties. In this work, a multi-scale approach to device simulation, capable to include ab-initio modelling of the interfaces in a computationally efficient way, is presented. As an application, p- and n-type monolayer-multilayer PtSe2 LH-FETs are investigated, considering design parameters such as channel length, number of layers and junction quality. The simulations suggest that such transistors can provide high performance in terms of subthreshold characteristics and switching behavior, and that a single channel device is not capable, even in the ballistic defectless limit, to satisfy the requirements of the semiconductor roadmap for the next decade, and that stacked channel devices would be required. It is shown how ab-initio modelling of interfaces provides a reliable physical description of charge displacements in their proximity, which can be crucial to correctly predict device transport properties, especially in presence of strong dipoles, mixed stoichiometries or imperfections.
Fig: Block diagram of the multi-scale procedure. Bulk DFT calculations of the materials forming the LH are performed using a plane wave basis. The resulting Hamiltonians are then projected onto MLWF and used as building blocks to construct a LH Hamiltonian with an arbitrarily long channel. The resulting LH Hamiltonian is finally used as input in NanoTCAD ViDES to simulate LH-FETs in far-from-equilibrium conditions.

Acknowledgements: This work has been supported by the European Commission through the Horizon 2020 Framework Program, Future Emerging Technologies QUEFORMAL project (contract n. 829035). The authors thank Dr. Alessandro Fortunelli for useful discussions.

In #Germany talks are for an advanced few nm #Intel #fab



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Oct 26, 2021

conference paper reached 400 reads

conference paper reached 400 reads

Bucher, M., J-M. Sallese, F. Krummenacher, D. Kazazis, C. Lallement, W. Grabinski, and C. Enz
EKV 3.0: An analog design-oriented MOS transistor model
In 9th International Conference on Mixed Design of Integrated Circuits and Systems
(MIXDES 2002)

Abstract:  The EKV 3.0 compact MOS transistor model for advanced analog IC design and simulation is presented. The model is based on the surface potential approach combined with inversion charge linearization. The ideal long-channel model is coherent  for  static  and  dynamic  aspects  including  noise.  The  ideal  model  is  extended  for  high-field  effects  in  deep submicron CMOS technologies. Scalability over channel length and width is achieved while retaining a reduced number of parameters. The EKV 3.0 model is applicable over a large range of CMOS technologies.  

Fig: Normalized source transconductance to current ratio (gm/ID) vs. normalized current, measured 
(markers) in saturation from various CMOS technologies, and analytical model.


Solving for #Silicon Shortages >> #Framework Laptop #DIY



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