[https://t.co/rrssJ7q5A5] Apple Unveils New M1 Pro, Monster M1 Max SoCs #semiconductor #intel #apple #customsilicon #competition #leadership #semi https://t.co/9wsFqWvLXN
— Wladek Grabinski (@wladek60) Oct 19, 2021
Like Thierry Breton, the president Emmanuel Macron wants #EU to double its#semi #production capacity. The #France and #Europe want to invest €6 billion and €40 billion respectively. [ @VIPress, #semiconductors, #chips] https://t.co/AzzG721WX9
— Wladek Grabinski (@wladek60) Oct 13, 2021
Webex link will be distributed to the registrant via email.
Organizer contact: John Choi (wonhochoi at micron.com)
Abstract:
In semiconductor technology development, it is desirable to pinpoint the source of defect or variation through electrical measurements, which are non-destructive and have much higher throughput than the traditional failure analysis. This can be achieved through machine learning which is a powerful tool for correlating the electrical characteristics to the nature of the defect/variation. However, a good machine is only possible with enough well-controlled training data, which is difficult to obtain experimentally. TCAD and SPICE simulations which are well-calibrated to experimental data are proposed to generate the training data.
In this talk, we will first demonstrate the use of TCAD to generate data to train machines to deduce the epitaxial layer thickness of Si p-i-n diodes and the workfunction and operating temperature variation of Ga2O3 Schottky Barrier Diodes, based solely on the measured electrical characteristics. We will emphasize the use of minimal domain expertise to obviate the difficulties in feature extraction. We will also demonstrate the techniques that are important to make the TCAD-trained machine applicable to predicting experimental data. SPICE-augmented ML will be demonstrated for detecting contact resistance degradation in inverters. Finally, we will discuss the use of TCAD-augmented machines to help reverse engineering and understand novel devices.
Speaker Bio:
Hiu Yung Wong is an Assistant Professor in the EE department, San Jose State University. He received his Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley in 2006. From 2006 to 2009, he worked as a Technology Integration Engineer in Spansion. From 2009 to 2018, he was a TCAD Senior Staff Application Engineer in Synopsys, during which he received the Synopsys Excellence Award in 2010. In 2021, he received the NSF CAREER award and the Newnan Brothers Award for Faculty Excellence.
His research interests include the applications of machine learning in simulation and manufacturing, cryogenic electronics, quantum computing, reliability simulations, wide bandgap devices (such as GaN, SiC, Ga2O3, and diamond) simulations, novel semiconductor devices design, and Design Technology Co-Optimization (DTCO). His work has produced 80 papers and 10 issued patents.
Call for Officer(s):
The Santa Clara Valley Chapter of the EDS is seeking candidates to apply for positions on the organizing executive committee for 2022. In particular we are looking for folks interested in becoming webmaster/communications director and secretary, although we welcome applications for treasurer, vice-chair, and chair as well. If you are interested in helping us organize technical talks and otherwise delivering value to EDS members in your local community, please email vijay_narasimhan@ieee.org, EDS SCV Chapter Chair, to express your interest.
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